Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on Yesterday, 13:02

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by RayeR

in Release Announcements

in Release Announcements

I'm skeptical to this bridge chaining approach. There are already boards with PCIe2PCI and PCI2ISA bridges without ISA DMA. I think if they can they would already implement it to bridges.

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Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on 2025-04-20, 01:03

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by RayeR

in Release Announcements

in Release Announcements

Interesting findings. Further stap maybe dump/download UEFI flashrom image, unpack, try to find SMI handler module and disassemble it to see if it interacts with detected IO ports... Maybe intel implemented this with intention but UEFI writers didn't implemented it then as it would be low priority …

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Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on 2025-04-19, 13:56

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by RayeR

in Release Announcements

in Release Announcements

Is the GPP_A7/PIRQA#/GSPI0_CS1# signal at the same ball position as LDRQ on older PCH? If so, I think it's leftover that someone forgot remove that connectin in schematic...

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Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on 2025-04-19, 03:15

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by RayeR

in Release Announcements

in Release Announcements

I can only point there are newer MBs with paraller port like this one https://www.gigabyte.com/Motherboard/Z370-HD3P-rev-10/sp#sp but no details if supports ECP mode. I don't have acces to such new HW to investigate myself... As I seen the crippled UEFI usually don't have any extra options for COM/ …

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Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on 2025-04-18, 16:01

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by RayeR

in Release Announcements

in Release Announcements

From the datasheet you linked, it seems the net meant for so-called "LDRQ0#" actually connects to the PCH's GPP_A7/PIRQA#/GSPI0_CS1# (per 300 series datasheet ). I wonder what SuperIO would be using that pin for, as the PCH no longer provides any LDRQ# signal nor have any 8237 controller in it... …

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Re: dISAppointment - LPC to ISA adapter - ISA on modern motherboards

Posted on 2025-04-18, 15:48

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by RayeR

in Release Announcements

in Release Announcements

I'm compiling a list on Github here (fork from original repository): https://github.com/AranVink/dISAppointment It's still a work in progress. Please change the status of my MB Gigabyte GA-P67A-D3-B3, it should be in working section. Here was a video prove it https://www.youtube.com/watch?v=ywgrP- …

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Re: Dual Pentium Pro Build Thread

Posted on 2025-04-18, 15:11

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I tested with Abit BE6 II modded BIOS but still no any POST code. Can somebody else report his experiences (with POST card) if unmodified BIOS can hangs so early that it can't send any POST code? Or if it is rather a HW bug on my adapter? I'll check it. Just a note that I tried to put the POST card …

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Re: Dual Pentium Pro Build Thread

Posted on 2025-04-17, 06:27

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by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I just quickly tried 6 Slot 1 MBs I have with stock BIOS and succes rate is not high: Abit AB-LX6 Vcc 3,3V, Award, no POST code intel AL440LX Vcc 3,3V, Phoenix, no POST code Jet-Way J-791BS Vcc 3,3V, Award, POST code C1 PC-chips M741 Vcc 3,3V, AMI, POST code 86, blank screen, but with PII code 86 …

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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

Posted on 2025-04-17, 02:07

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

New version 5.81b3 reports both CPU names in consistent way:

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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

Posted on 2025-04-15, 19:40

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

I don't bother much, it's just my for fun personal project. M$ tighten rules with every new windows version and I don't have enough time to fight against. AFAIK you have to be some kind of commercial subject to be able get drivers signed by M$. I personally still run XP-SP3 as main OS (and use CPUID …

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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

Posted on 2025-04-15, 18:19

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Probably due to unsigned kernel driver - w7/w10-x64 enforces driver signing and I, as an individual, cannot sign my driver myself so it wouldn't run under W10 in normal mode, needed to enable test mode anyway. My tools is primary targeted for DOS but I made it multiplatform for Win and Linux too. …

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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

Posted on 2025-04-15, 12:29

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

OK, I understand. My CPUID utility use similar approach. [link removed on red-ray request, can be found on my homepage in user profile] It displays CPU name string if available and also displays a CPU database name that is my own description that contains more details like socket, voltage, …

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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

Posted on 2025-04-15, 04:29

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Here's screen of my core i7-2600K, yes I have HT disabled because it disturbs some singlethreads apps. There are 2 different CPU names reported that looks a bit confusing...

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-14, 12:46

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

If someone would like to programm a GIF encoding module in assembler it could be used instead of PCX. I think that PCX is much simpler format (using RLE compression?) than GIF. I think it's not necessary, everybody can use some external utility to convert PCX to any other bitmap format...

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-14, 00:26

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Here's the hotfix for 486DLC/SLC, so I finally got it benchmarked 😀

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-13, 18:44

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Btw the source was given by Vladimir in 2006 but it stucked in private closet 19 years, without any change...

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-13, 15:38

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Here https://github.com/bttrx/speedsys no *.pas there, build batch calls TASM.

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-13, 12:10

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Meanwhile it happened that one guy on other forum, seeing by dbg effort, has just uplodad sources of Speedsys 4.79 WIP on Github under GPL (as author permitted), huh! He got it a long time ago from Vladimir when his mail worked yet. But no changes was made for the whole time, waiting for now. …

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-12, 03:46

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Yeah, I traced it via DarkDebugger (need stepping, breakpoint at I/O didn't work). You can see that Speedsys attempts to read config reg. FEh from port 22/23h that is not valid for this CPU so it's passed to bus cycle and crashed the chipset. When I skipped this I/O operation Speedsys started and …

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Re: 486DLC internal cache and Speedsys

Posted on 2025-04-11, 04:47

by

by RayeR

in Marvin \ General Old Hardware

in Marvin \ General Old Hardware

Damn, I'm screwed. Tx486DLC doesn't have CR4 neither debug extension, it has only DR0-7 so I can't set breakpoint on IO access :( I also search and look for some datasheets and it seems there's no difference in CPU config regs range CO-CFh but who knows what else Speedsys is trying to read. I hoped …

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