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Re: Can 32-bit x86 programs explicitly use IP?

Posted on 2024-04-07, 21:43

Can 32-bit x86 programs even explicitly use IP instead of EIP(which uses masking on the high 16-bits when loaded this way) during fetching (like SP vs ESP)? The decision whether IP or EIP is used as offset to CS when fetching instructions is the "D/B" bit of the code segment descriptor. If you call …

Can 32-bit x86 programs explicitly use IP?

Posted on 2024-04-07, 20:28

Can 32-bit x86 programs even explicitly use IP instead of EIP(which uses masking on the high 16-bits when loaded this way) during fetching (like SP vs ESP)? Or is it always 32-bit on such platforms (16-bit loads simply set the top 16-bits to 0, 32-bit increments always overflow to the upper 16-bits …

Re: ESS ES1688 PnP ROM dump

Posted on 2024-04-05, 07:05

What you're talking about is true for PCI but not ISA PnP which the ES1688 PnP would be. Isn't ISA PnP a subset of PCI PnP? Using ports 8-bit C000-FFFF and 8-bit CF8 and CFA I/O ports? https://wiki.osdev.org/PCI#Configuration_Space_Access_Mechanism_.232 (PCI '1.o'?) Can't find any documentation …

Re: i430fx/i440fx APM?

Posted on 2024-03-28, 17:52

Just added an extra mapping of the i82347 mapping to address base+2 and base+3 of the PCS chipset. Then I also added mapping writes at the PCS base address +0 to write C0 to address +2 and the value written to address +3(thus the F0h write writes to the first register of the i82347). It also adjusts …

Re: i430fx/i440fx APM?

Posted on 2024-03-28, 13:12

Added an extra 'green button' option to the settings to trigger EXTSMI# on the chipset (both i82347 and PIIX/PIIX3 chipsets). i82347 will only take effect if 'activated' by writing it's registers after a hard reset (which is a PCI reset and during poweron). So both ways can work in harmony with each …

Re: i430fx/i440fx APM?

Posted on 2024-03-17, 20:04

Shutting down Windows 95 also writes F0h to said port. Other issued states locks up the machine with a black screen (suspend I think), or resume from a black screen with a key press. This is what I get on said PCS ports when Windows 95 (and BIOS) boots up and shuts down the machine: 00:00:01:16. …

Re: More extended CPU testsuites like test386.asm?

Posted on 2024-03-17, 19:14

57:15:11:45.08304: >>> Done! It's finally finished. So 2 days 9 hours and 15:11:45.08304 minutes to complete. So roughly 2.3 days to complete. Results: porte9_baresifter_20240314_0939.zip The command for the analyzer is almost correct: It's supposed to be: cargo run -- --bits 32 Edit: Nonetheless, …

Re: i430fx/i440fx APM?

Posted on 2024-03-17, 16:10

But looking at what the BIOS does doesn't match anything sane with what the program is requesting and what the BIOS writes to register address 0 on said device? The port written by the request is at 13F0 (configured to 13F0) with value F0 written to that address. Looking at the address x0 on said …

Re: i430fx/i440fx APM?

Posted on 2024-03-17, 12:26

I added some logging, I see the following before the i440fx memory testing: Read from 21h, base address 20h, 16-bytes size. Write to 21h, value FFh x2. ... Write to 21h, value FEh. Write to 29h, value 20h x2. Write to 21h, value FFh. Write to 21h, value 00h. Read from 21h. Write to 21h, value B8h. - …

Re: i430fx/i440fx APM?

Posted on 2024-03-16, 21:17

So the function call 5307h is interesting. It sets PIIX Programmable Chip-Select Control register to I/O port 13F0 (selected by register 78h/79h), then writes 13F0 to it, using byte operations? That's supposed to be the powerdown sequence? What chip is it using on PIIX programmable chip-select? …

Re: i430fx/i440fx APM?

Posted on 2024-03-16, 19:18

OK. I've implemented the chip according to the found documentation fully (minus some CPU and outputs being handled by hardware (they're calculated though). I don't see SMM using it though (using a test program from https://github.com/crgimenes/shutdown using quit.com) I look at https://bochs. …

i430fx/i440fx APM?

Posted on 2024-03-15, 08:04

Does i430fx/i440fx chipsets have APM for powering the device off? If so, how does this work on real hardware (inside SMM)? Edit: Some more searching... https://github.com/cirosantilli/ralf-brown-interrupt-list/blob/master/inter61d/PORTS.A ----------P00260027-------------------------- PORT 0026-0027 …

Re: More extended CPU testsuites like test386.asm?

Posted on 2024-03-14, 15:39

Anyone knows if it's possible to get the search engine's filtered prefix detection with skipping to work with the Baresifter analyzer program? Right now it would give a lot of issues with the skipped and undetected prefixes I think (results are still running inside UniPCemu for a few days at least)? …

Re: More extended CPU testsuites like test386.asm?

Posted on 2024-03-13, 17:18

Improved the Baresifter program a bit. Added 2 bitmask parameters: detect_prefixes and used_prefixes. Both default to 0xFF (use all available) for compatibility. Now the two settings work as follows: - The bit in the variable represents the prefix group (bit 0=LOCK/REPNE/REP, bit 1=segment overrides …

x86 UD1 parameters?

Posted on 2024-03-12, 20:31

What are the actual parameters of an UD1 instruction? https://www.felixcloutier.com/x86/ud It says it's "0F B9 UD1 r32, r/m32". But is it really only r32,r/m32 or also r16/rm16? So basically full modr/m decoding and fetching in 16/32-bit mode, but no actual use of it (due to throwing #UD for the EU …

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