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KBC Output Port, Port 92h, and A20 gate

What happens on real hardware if you enable A20 on the KBC Output Port, but then disable it on Port 92h? Does it stay enabled (the two are OR'ed) or disabled (the two are AND'ed)? And what happens when you do it the other way around - disable A20 on the KBC Out Port and then enable it on Port 92h? …

Re: MPU-401 IRQ's...

How does the Reset command (0xFF) behave on the SB16's built-in MPU-401? The SB16 documentation linked in this thread says it generates an ACK, but is unclear on whether or not it generates an IRQ.

Re: MPU-401 IRQ's...

The behavior makes me presume that the UART itself has no FIFO, and the FIFO instead stands between the MIDI input and the UART, so bytes enter into the FIFO, and if there is no byte pending to read, one of them is pushed ahead and the IRQ raised. After the byte is read, the IRQ is cleared, and if …

Re: MPU-401 IRQ's...

Thank you very much! The ESS one is especially useful, as for one, it clearly calls the MPU-401 queue a FIFO, and also talks about a transmit FIFO as well. Now I need to read the NS16550 UART datasheet to see how FIFO IRQ's behave there (maybe I'm misrememebring something), becaue while this is not …

MPU-401 IRQ's...

Since a friend of mine and I are working to add MIDI input to 86Box and are wondering, under what circumstances does the MPU-401 issue an IRQ... Is it only in intelligent mode or also in UART mode? And is it on every byte received, or, like an UART with FIFO would do, only when the queue is full?

Re: PCEm. Another PC emulator.

Are there any decent forks of this project? There sure is! : ) 86box is the most notable one. It's a bit more experimental though, so be aware that it's often not quite as stable. That was maybe true in the beginning, but noawadays, if anything, 86Box has stricter requirements for what is added …

Re: (S)VGA address calculation for latch

Whatever plane has its bit clear in the colour no care register, will be always assumed to match even if it does not, so if all 4 planes are clear in that register, then you will read a 0xFF as everything will be assumed to match. But yeah, aside from that, your implementation is correct now.

Re: (S)VGA address calculation for latch

From how I understood (and as of this morning's 86Box commit, implemented!) read mode 1, it does 8 pixels one by one, and for each pixel, compares each bit (which is on a separate plane) with the corresponding plane's bit in the color compare register, and if its corresponding bit in the color don't …

Re: (S)VGA address calculation for latch

I think you're the only one who has implemented read mode 1 somewhat correctly, though I notice that VGADOC's VGAREGS.TXT says this: 3CEh index 2 (R/W): Graphics: Color Compare Register bit 0-3 In Read Mode 1 each pixel at the address of the byte read is compared to this color and the corresponding …

(S)VGA address calculation for latch

How do I calculate it correctly? I know that I have to AND it with the mask that depends on GDC register 6 bits 7 and 6, so let's say I have 64k at A000 set, that means I have to do: address &= 0xffff Then, assuming this is not chain 2 or chain 4, I have to do: address <<= 2 But what next? I know I …

Re: Logitech C7 serial mouse power-up sequence

I just got reports back from a person who tested the real mouse for me, and basically, when you set DTR active, the mouse raises DSR (and you get a MSR interrupt from the serial port if the serial port is appropriately configured), and when you set RTS active, the mouse raises CTS (and you get a MSR …

Logitech C7 serial mouse power-up sequence

What exactly does the Logitech C7 serial mouse do on the power-up sequence? I mean, the sequence appears to be, set DTR active, then set RTS active, then wait for something, but for what? 86Box's emulated mouse right starts a timer when that happens, that sends the 0x4D ('M') but Windows 2000 (and …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

The number of wait states introduced by a DRAM refresh can be anything from 0 to 6 cycles (assuming no wait state for the refresh memory access itself). The zero case happens when the bus would otherwise be idle. Other cases depending on when the refresh happens with respect to the adjacent CPU bus …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

So far it appears to run fine, except that the credits have no sound but that's because the emulation of the PIT and the PC speaker leaves a lot to be desired, so it's on my list to be eventually either rewritten or ported from DOSBox where I heard PIT mode 1 (which I presume the credits use) works. …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

OK, fixed the DMA channel 0 so that it only triggeres refresh read when the DMA is programmed to read or write, reenigne's blog says the BIOS takes care of that, and my logging has verified that that indeed happens, so that's one thing settled. However, my other question remains - what's with that …

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