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Re: (S)VGA 256-color shift and Chain 4

But then why is it expecting to be in Chain 4 without Chain 4 being set? Edit: So then Shift 256 is OR'ed with Chain 4? That might be true but then wouldn't the Windows 95 boot screen and Wolfestein 3D both break since I have observed both of them using 256-color planar mode? Edit #2: Reading the …

Re: (S)VGA 256-color shift and Chain 4

The OS/2 ET4000AX driver also writes to sequencer register 0E (which is entirely undocumented!), setting bit 1. The Windows 3.x ET3000AX driver sets bits 4 of attribute register 0x16. Edit: And I'm running the actual BIOS'es as well. What I see, with both of those drivers, is the card being put into …

(S)VGA 256-color shift and Chain 4

On real hardware, does the the (S)VGA 256-color shift (GDC register 5 bit 6) force the video memory into Chain 4 mode regardless of sequencer register 4 bit 3? Or is that a Tseng-specific thing? Because I have two different Tseng drivers, the Windows 3.1 driver for the ET3000AX and the OS/2 "SVGA" …

Re: VGA difference of blacks?

If SVGA monitors use the same specifications as (non-Japanese) NTSC, then blanking would be at 0%, while the active display (black to white) levels would be at 7.5% to 100%. But I'd look up actual (S)VGA documentation for that instead, perhals look up the voltage range and convert it to %, and then …

Sound Blaster filters and CD Audio

Does the Sound Blaster apply any of its filters (low-pass, treble, and bass - not all Sound Blaster versions have all of these) to the CD Audio it gets by cable from the drive? Edit: And what about OPL? Do those filters get applied to the OPL?

Re: PS/2 mouse on IBM PS/2 models 25-8086 and 30-8086

So, if I understand correctly, on PS/2 Model 25-8086 and 30-8086, keyboard, mouse, and RTC alarm are all on IRQ 1, and IRQ 1 always issues INT 71h, whose BIOS handler then demultiplexes it to INT 70h, IRQ 1 INT (with base read from port 63h), and INT 73h. Looks like I'll need to add this special …

Re: PCEm. Another PC emulator.

leileilol wrote: The dynarec's improved much since 2016.... But the new one has some regressions that I'd say are quite important, which have been reported to the developer but have not been fixed yet.

KBC Output Port, Port 92h, and A20 gate

What happens on real hardware if you enable A20 on the KBC Output Port, but then disable it on Port 92h? Does it stay enabled (the two are OR'ed) or disabled (the two are AND'ed)? And what happens when you do it the other way around - disable A20 on the KBC Out Port and then enable it on Port 92h? …

Re: MPU-401 IRQ's...

How does the Reset command (0xFF) behave on the SB16's built-in MPU-401? The SB16 documentation linked in this thread says it generates an ACK, but is unclear on whether or not it generates an IRQ.

Re: MPU-401 IRQ's...

The behavior makes me presume that the UART itself has no FIFO, and the FIFO instead stands between the MIDI input and the UART, so bytes enter into the FIFO, and if there is no byte pending to read, one of them is pushed ahead and the IRQ raised. After the byte is read, the IRQ is cleared, and if …

Re: MPU-401 IRQ's...

Thank you very much! The ESS one is especially useful, as for one, it clearly calls the MPU-401 queue a FIFO, and also talks about a transmit FIFO as well. Now I need to read the NS16550 UART datasheet to see how FIFO IRQ's behave there (maybe I'm misrememebring something), becaue while this is not …

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