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Sound Blaster filters and CD Audio

Posted on 2020-10-19, 12:23

Does the Sound Blaster apply any of its filters (low-pass, treble, and bass - not all Sound Blaster versions have all of these) to the CD Audio it gets by cable from the drive? Edit: And what about OPL? Do those filters get applied to the OPL?

Re: PS/2 mouse on IBM PS/2 models 25-8086 and 30-8086

Posted on 2020-10-05, 19:18

So, if I understand correctly, on PS/2 Model 25-8086 and 30-8086, keyboard, mouse, and RTC alarm are all on IRQ 1, and IRQ 1 always issues INT 71h, whose BIOS handler then demultiplexes it to INT 70h, IRQ 1 INT (with base read from port 63h), and INT 73h. Looks like I'll need to add this special …

Re: PCEm. Another PC emulator.

Posted on 2020-07-12, 02:56

leileilol wrote: The dynarec's improved much since 2016.... But the new one has some regressions that I'd say are quite important, which have been reported to the developer but have not been fixed yet.

KBC Output Port, Port 92h, and A20 gate

Posted on 2020-02-08, 19:31

What happens on real hardware if you enable A20 on the KBC Output Port, but then disable it on Port 92h? Does it stay enabled (the two are OR'ed) or disabled (the two are AND'ed)? And what happens when you do it the other way around - disable A20 on the KBC Out Port and then enable it on Port 92h? …

Re: MPU-401 IRQ's...

Posted on 2020-01-22, 05:03

How does the Reset command (0xFF) behave on the SB16's built-in MPU-401? The SB16 documentation linked in this thread says it generates an ACK, but is unclear on whether or not it generates an IRQ.

Re: MPU-401 IRQ's...

Posted on 2020-01-04, 01:43

The behavior makes me presume that the UART itself has no FIFO, and the FIFO instead stands between the MIDI input and the UART, so bytes enter into the FIFO, and if there is no byte pending to read, one of them is pushed ahead and the IRQ raised. After the byte is read, the IRQ is cleared, and if …

Re: MPU-401 IRQ's...

Posted on 2020-01-03, 16:55

Thank you very much! The ESS one is especially useful, as for one, it clearly calls the MPU-401 queue a FIFO, and also talks about a transmit FIFO as well. Now I need to read the NS16550 UART datasheet to see how FIFO IRQ's behave there (maybe I'm misrememebring something), becaue while this is not …

MPU-401 IRQ's...

Posted on 2020-01-03, 03:02

Since a friend of mine and I are working to add MIDI input to 86Box and are wondering, under what circumstances does the MPU-401 issue an IRQ... Is it only in intelligent mode or also in UART mode? And is it on every byte received, or, like an UART with FIFO would do, only when the queue is full?

Re: PCEm. Another PC emulator.

Posted on 2019-12-23, 01:44

Are there any decent forks of this project? There sure is! : ) 86box is the most notable one. It's a bit more experimental though, so be aware that it's often not quite as stable. That was maybe true in the beginning, but noawadays, if anything, 86Box has stricter requirements for what is added …

Re: (S)VGA address calculation for latch

Posted on 2019-12-06, 04:03

Whatever plane has its bit clear in the colour no care register, will be always assumed to match even if it does not, so if all 4 planes are clear in that register, then you will read a 0xFF as everything will be assumed to match. But yeah, aside from that, your implementation is correct now.

Re: (S)VGA address calculation for latch

Posted on 2019-12-05, 00:25

From how I understood (and as of this morning's 86Box commit, implemented!) read mode 1, it does 8 pixels one by one, and for each pixel, compares each bit (which is on a separate plane) with the corresponding plane's bit in the color compare register, and if its corresponding bit in the color don't …

Re: (S)VGA address calculation for latch

Posted on 2019-12-04, 04:23

I think you're the only one who has implemented read mode 1 somewhat correctly, though I notice that VGADOC's VGAREGS.TXT says this: 3CEh index 2 (R/W): Graphics: Color Compare Register bit 0-3 In Read Mode 1 each pixel at the address of the byte read is compared to this color and the corresponding …

(S)VGA address calculation for latch

Posted on 2019-12-03, 20:33

How do I calculate it correctly? I know that I have to AND it with the mask that depends on GDC register 6 bits 7 and 6, so let's say I have 64k at A000 set, that means I have to do: address &= 0xffff Then, assuming this is not chain 2 or chain 4, I have to do: address <<= 2 But what next? I know I …

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