MVP3 chipset uses 8bit tag ram so cacheable size = cache size * 256 if dirty bit is disabled (default) or cache size * 128 if dirty bit is enabled. So, 512KB * 256 or 128 would be 128MB or 64MB of cacheable memory area. What is a "dirty bit?" And, does this mean all MVP3 boards max out at 128MB of …

I have a VIA MVP3 board with 512KB memory cache. From how I understand it, whether 128MB (or more or less) of RAM that can be utilized without detriment is dependent on the tag ram modules installed. I don't even know which ones those are, though I'm assuming the two long skinny ones because they …

Nice find, just desolder the battery and buy a holder for the coil cell to make things easy but I wouldn't cut it. I had a PB just like this and you only get the basics with no cache. Can you illustrate the holder for the coil cell technique of yours in more detail? This'll be my first ad hoc " …

I've been itching to build a Socket 7 machine like the one I had when I graduated college, but I couldn't pass on this 486 for $10 (also picked up an early 80's Compaq Portable for $10, couldn't pass that up either!) This 486 is from 1994. My parents bought a 486SX during my senior year of high …

Greetings and happy new year! Been reading enough on this sweet forum that I had to register. Lots of info and insight which I'll definitely have need for. I'm planning to build a 90s Socket 7 system for fun; have some ideas and I'm sure some more will come from this forum. I just jumped into full …