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Re: MartyPC

Ok, it took me a little longer than expected, but MartyPC 0.2.0 is finally out. https://github.com/dbalsom/martypc/releases/tag/0.2.0b The changelog is pretty enormous but the main features are: New Display System: multiple scaling options, multi-window and multi-adapter support, fullscreen, shaders …

Re: MartyPC

Thanks to the assistance of coldbrewed I now have nightly builds of MartyPC available. These are currently based on the 0.2 branch with EGA support. It's a little convoluted downloading them, but the process is basically go to the actions tab: https://github.com/dbalsom/martypc/actions Click the …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

What about the 8259 IRR register? UniPCemu has IRR2 raised (it's parallel interrupt lines), so the line is actually raised. But the IMR register bit 2 is s, so the IRR isn't set somehow? IMR is BCh. If you turn off vsync interrupts in the CRTC, then I assume CRTINT is not produced. Therefore you …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

This has some additional interesting implications. Since the ISR bit is driven by CRTINT from the CRTC and not the VSYNC pin, if we disable interrupts it would seem we actually can't detect vsync at all? Other than reading the Input Status #0 register of course? my statement was directly about the …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

Good catch. The input status #0 register is implemented via 74LS367 hex bus driver. CRTINT from the CRTC goes directly here, and mapped to bit 7. I don't see it inverted anywhere. CHIPS documentation on their clone CRTC says that CRTINT is active-high. Wouldn't be the first time IBM documentation …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

IRQ2 is raised when vertical retrace starts, with Vertical Retrace end register bit 4 set and bit 5 cleared (setting the flipflop). It's set and not changing afterwards? Lower it at the end of vertical retrace. I know that seems counterintuitive since there's a bit to lower it as well... EDIT: I'm …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

UniPCemu's CPU and DMA both use the same kind of memory handling basically. Stuff like delays are handled in exactly the same way (with regards to the waitstates at least). The CPU checks when starting any memory transfer a variable that indicates which device has bus control (PCI(IDE) or DMA or …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

One fun thing about DMA to VRAM is that technically, we need to account for the CGA wait states when performing the transfer. The DMA controller obeys the READY line in a similar way that the CPU does. I don't emulate this yet - just means that things will get put in VRAM faster than they should on …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

One fun thing about DMA to VRAM is that technically, we need to account for the CGA wait states when performing the transfer. The DMA controller obeys the READY line in a similar way that the CPU does. I don't emulate this yet - just means that things will get put in VRAM faster than they should on …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

Does it instruct MS-DOS to write directly the read file contents into VRAM? I see lots of INT 21h function AX=1A1Ah followed by INT 21h function AX=2121h (memory at DS:BX=2)? Yes, it does. It sets the map mask register to isolate the appropriate plane, then Int 21h 3F to read two blocks of 8000h …

Re: EGA FLAND maps 0/1 loading issues in UniPCemu

Nothing special that I can see - but I suspect you might be making some assumptions about text mode. Normal text mode puts the CRTC in word mode, with the sequencer and graphics controller in Odd/Even mode FLAND puts the CRTC in byte mode, and the sequencer and graphics controller are set for …

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