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Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 14:34

Edit: What about the other (un)conditional jump instructions and call instructions? Do they delay the BIU 6 cycles as well? Taken conditional jumps and LOOPs (including JCXZ): 6 cycles. Near/short JMP: 6 cycles. Indirect JMP (i.e. "JMP CX"): 3 cycles. Indirect CALL (i.e. "CALL CX") and near CALL: …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 14:11

I've modified the BIU to take those idle cycles without increasing the T-state. I've modified opcode 0xEB to use 16 execution cycles, of which the first 6 cycles idle the BIU, keeping the same T-state. That looks a bit better. Next problem: the bus going idle only happens after a T4 state completes …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 13:04

That's actually a jump being executed(JMP 026C). It uses 15 CPU EU cycles, of which 15 cycles BIU disabled 15 cycles seems too long to disable the BIU here. As I said, a real 8088 only idles the bus for 6 cycles here, so prefetches can't be disabled for more than 8. Are the T-states to be kept the …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 12:19

When it has nothing to do(no BIU memory/BUS requests and prefetch buffer is full), it will execute a NOP cycle(BUS being idle, now reporting "BIU --" instead of T-state. So what's going on in your latest log between lines 3260 and 3277? There are four bus cycles (16 CPU cycles, counting up T1..T4) …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 11:34

It's essentially the same? Idle is/becomes T1 when there's something to do(first state of transfer), idle otherwise. On the real hardware, the T1 state is when the address to access is placed on the bus. So if the EU needs to start a bus access, it will be able to if the current bus state is idle …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-03, 06:54

So if I understand it correctly, I should make it keep T1 state while nothing is to be done? Thus starting any transfers(Instruction or data) the very same cycle something's ready to process. So keep it stuck at T1 state until something's requested(or DMA takes over) instead of the current inactive …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-02, 20:46

The EU is busy all that time, while the BIU releases the bus after the last instruction/memory fetch(modr/m), then proceeds to do nothing(walking T-states without fetching anything from memory or storing anything. The DMA controller(s) are free to take control of the BUS anytime. Once the prefetch …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-02, 18:43

Is that what you meant? Closer... Now, if you trim out everything except the bus state (T1-T4/S0-S4 etc), the instruction and the bus transfer type/address/data you'll have something that's much more compact and much closer to the bus sniffer's output. Then it would be easier to compare the two. …

Re: UniPCemu cycle accurate 8088 implementation

Posted on 2017-05-02, 09:49

Here's the latest log on the standalone executable of the 8088 MPH credits: https://www.dropbox.com/s/byny06he285zvfq/debugger_8088MPH_credits_20170502_1100.zip?dl=0 It now contains the new S-state and T-state logs. This log shows the same problem as the last one - the prefetch of the second byte …

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