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Re: c++ divides signed int using sar?

SAR of -1 does not clear the MSB. It copies the sign bit into the next bit, and retains the sign bit. Also, your comments don't match your code. SHR EDX, 1F = 1, not 7FFFFFFFF. and LEA EAX, [EDX+EAX-1] isn't encoded as 8D 04 02, it's 8D 44 02 FF.

Re: JMP to call gate?

Yes, if you have pushed the return address, perhaps as a tail-call optimisation (i.e. call to a function which links to a leaf function), then you can jump through the gate to save the size of the return instruction.

Re: Stack overflow/underflow on x86?

Just been thinking: Are offsets 33-bits or 32-bits+carry on 32-bit x86 processors? Otherwise, a overflow during 32-bit accesses wouldn't be detected, as it silently wra[s back to offsets 0-2? The 80286 faulted on word accesses past 0xFFFF, so it had to have a least 17-bits to detect that. It might …

Re: Stack overflow/underflow on x86?

A push with SP=1 (for example) will fault in the same way, because the stack pointer will be reduced to FFFF, and then the write will be attempted, causing an address overflow. The same thing happens for a dword push with SP=1-3. SP=0 is fine - it will subtract to FFFC and then write as usual.

Re: x86 CPU emulators vs Intel patents?

I am not aware of any patents that would restrict the use of emulation of the kind that we do, since it is all "clean room" by virtue of having no access to microcode. I think that the bigger problem is the NDAs that stop people like me from describing specific things like obscure instruction …

Re: test386.asm CPU tester

SAR should set AF not clear it when count != 0. Looking at 8-bit SHL, you don't need the special-casing for count=0x10 and 0x18. They should both behave like count=8. OF will be set as expected, regardless of the count, so: mov al,0x40 shl al, 0x10 will still perform the shift, AL will be zero, and …

Re: test386.asm CPU tester

superfury wrote: Just fixed the auxiliary flag to set(shl/shr) or clear(sar) on maskcnt!=0. Now shr crashes because of an invalid carry flag? For SAR, auxilliary carry flag is always set for CPUs prior to Pentium 2 if count &0x1F != 0.

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