Re: Memory size, cacheable range and performance. Socket 5/7
Posted on 2018-10-08, 02:18
I thought increasing the L2 cache on an MVP3 board was for the purpose of increasing how much RAM could be cached? I too don't fancy ALi SS7 boards because of the confusion around K6-2/3+ support. I use a 2 MB MVP3 board by Tyan in one of my builds. I know Epox and Tyan make 2 MB revisions that, …