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Re: UniPCemu IBM AT emulation FDC/DMA issues?

Posted on 2018-01-26, 21:23

Just tried running the IBM AT diagnostic disk(ATADG207.IMG file), but after following it(it says the CMOS battery has been disconnected) it gives me a 0152 ERROR - SYSTEM BOARD? Filename 468-AT Diagnostcs error on CMOS cleared.jpg File size 9.9 KiB Downloads No downloads File comment Diagnostics …

PC RTC/AT CMOS/Compaq CMOS Y2K-compatibility?

Posted on 2018-01-26, 14:23

There's the XT RTC, which has an (updated on rollover, software-set only?) year byte, while the AT docs say that it has a century byte? But some documentation I've found says it doesn't update? What happens on the AT and Compaq Deskpro 386 when the year byte of the RTC rolls over? And what about the …

Re: UniPCemu IBM AT emulation FDC/DMA issues?

Posted on 2018-01-26, 00:27

Just managed to fix various CMOS calculations(which were overflowing when setting the century byte(0x32th byte in CMOS RAM) to a large enough value). I've also added a support setting(in the file only) for supporting binary vs BCD-style century bytes(binary style only used when the program writes a …

Re: UniPCemu IBM AT emulation FDC/DMA issues?

Posted on 2018-01-25, 13:27

After some fixing on the FDC Read ID command to terminate correctly(correct results, errors and actually raising the required IRQ(which was forgotten)). Now MS-DOS 6.22 starts booting from the floppy disk on the IBM PC/AT! :D Edit: Eventually, it will fault and simply recalibrate(&sense interrupt), …

Re: UniPCemu IBM AT emulation FDC/DMA issues?

Posted on 2018-01-25, 10:48

Just modified the DMA Page register logic to behave in a more controller-like way(remapping 80-87 and 88-8F to the two controllers based on the controller number instead, halving the code size(and readability). DMA emulation: https://bitbucket.org/superfury/unipcemu/src/ …

Compaq Deskpro 386 CPU emulation issues?

Posted on 2018-01-25, 02:38

A simple new thread for my latest problem(AT BIOS booting floppy disks). DMA is still incorrectly initialized(filled with AAAAh values except FEh for page registers(except final being zeroed). I see it (when booting) executing commands 3,7,8 and A? No errors(except uninitilized BIOS settings) are …

Re: Cycle-accurate 8042/PS/2 keyboard emulation?

Posted on 2018-01-25, 00:30

I'm running the 06/10/85 type 2 motherboard(6MHz 80286) BIOS ROM from minuszerodegrees. Edit: Hmmm... Something's odd: the BIOS reads the entire result, including the AAh result from the buffer, then executes keyboard enable on the 8042. Then at the stuck keys check it finds the filled 8042(0xAA …

Re: Cycle-accurate 8042/PS/2 keyboard emulation?

Posted on 2018-01-24, 22:47

Vladstamate, can you see if there's a problem with the 8042/PS/2 keyboard combo? Somehow the BIOS fails at the Keyboard Reset(0xFF command), which sends both bytes during the initial loop(s), only to be counted as an error by the BIOS? Why would it be giving a AA 301-Keyboard error? Edit: http:// …

Cycle-accurate 8042/PS/2 keyboard emulation?

Posted on 2018-01-24, 19:17

I'm currently trying to get my 8042&PS/2 keyboard emulation running without errors, but currently it's giving a AA-301 Keyboard error? 8042 emulation(BUS interface and Transfer timing): https://bitbucket.org/superfury/unipcemu/src/188f24bb7815ceb77c3b37b6e7fe8d54bf340a6f/UniPCemu/hardware/8042.c?at= …

Re: Unaligned memory access and bus width

Posted on 2018-01-24, 09:51

Just looked at the source code for the 303 error. It only seems to be used during POST 38h, which is a keyboard/8042 controller i/o test(test2.asm line 1017)? Edit: After fixing the PS/2 keyboard being reset when enabling the First PS/2 Port on the AT+, it now continues on to try and reset the PS/2 …

Re: Unaligned memory access and bus width

Posted on 2018-01-24, 06:40

Afaik it's like the 286: 2 T-states for each memory transaction for aligned byte/word/dword. https://www.google.nl/url?sa=t&source=web&rct=j&url=https://eng-old.najah.edu/sites/eng-old.najah.edu/files/documentation_4.doc&ved=2ahUKEwji2YjI-e_YAhVDPBQKHdxTDLgQFjAAegQICxAB&usg= …

Re: Effect on POP (E)SP on the stack pointer?

Posted on 2018-01-24, 00:28

Address size override has no effect on that? SP/ESP is determined by SS descriptor size(big bit) only? http://www.logix.cz/michal/doc/i386/chp17-01.htm The only way the address size operand has effect with push/pop is with the r/m data pointing to memory, e.g. pop [cs:0001] vs pop [cs:00000001] ( …

Re: Unaligned memory access and bus width

Posted on 2018-01-23, 22:48

Just cross-referenced with the AT BIOS source code. It seems the second FDC to give the Sense Interrupt ST0=D1, but C1 is given by my emulator instead, causing it to abort in error? @line@address:desc @329> after:interrupt(fdc?) @f000:0000217b. Then: call 259f(WAIT_INT). WAIT_INT allows 0us response …

Re: Effect on POP (E)SP on the stack pointer?

Posted on 2018-01-23, 22:45

Whoops, my bad at my code example. You're right. So, if you don't watch 9ut mixing 16/32-bit code, you can set the high word of ESP corrupted(cleared in this case of 0verflow) due to the 32-bit code mixed with 16-bit code and pop sp combined with that case, even though that won't happen when using …

Re: Effect on POP (E)SP on the stack pointer?

Posted on 2018-01-23, 19:37

Just realized something: imagine the following running(with a 32-bit stack attribute size): MOV ESP,FFFFFFFC MOV [SP],FFFC POP SP That would cause ESP to become an invalid FFFC instead of FFFFFFFC? The overflow from the add is still applied, but the low 16 bits gets mixed in? Thus invalidly clearing …

Effect on POP (E)SP on the stack pointer?

Posted on 2018-01-23, 10:32

When executing a POP SP or POP ESP, what's in the resulting stack pointer(ESP) register? The documentation says (E)SP is incremented after reading it, so that would mean that (E)SP is loaded from the bottom of the stack, and that value that's read is incremented by 2 or 4. So (E)SP actually contains …

Re: Unaligned memory access and bus width

Posted on 2018-01-22, 14:15

Eventually just took out my MS-DOS 5.0a disk image and am now using it to format the disk image. Then it's back to MS-DOS 6.22 to copy the OS and finally convert the disk image to a static disk image to copy over all files that were on the old disk image. Still odd that MS-DOS 6.22 completely fails …

Re: Unaligned memory access and bus width

Posted on 2018-01-22, 12:41

I've just tested(using the #11h DMA test routine of the IBM AT BIOS 6MHz(2nd revision motherboard emulated)) and modified the Intel Inboard 386/AT to apply the following clocks (since I can't find any reference actualy saying the exact waitstates used on the AT board. The XT board does have it's …

Re: Unaligned memory access and bus width

Posted on 2018-01-22, 02:07

Thinking about it: what happens when a word is read/written within a modulo 4 block on a dx? Will it be read in 1 cycle(also following my mod 4 rule) always? Or will e.g. a word from offset 1 be read/written in 1 cycle(no modulo 4 crossed and 4 address lines are supported on the DX)? Hmmmm.... …

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