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Re: Unaligned memory access and bus width

Posted on 2018-01-22, 01:20

Essentially, DON'T read entire 16-bit/32-bit data from RAM/hardware, but instead only read the higher 32-bit byte(s) until it reaches the mod 2(386sx) or mod 4(386dx) point. Read the rest in the same way on the next cycle(s). 32-bit read from address 1/2/3 doesn't actually read from addresses …

Re: Unaligned memory access and bus width

Posted on 2018-01-22, 00:50

Looking some more, you're right: The 80386 does up to 2 back-to-back cycles with operands crossing 32-bit offsets: https://books.google.nl/books?id=-pz8rvnhFDkC&pg=PA176&lpg=PA176&dq=80386+byte+enable+lines&source=bl&ots=HKiMWf3ZNT&sig=xwC_zTrClMeTsXxWkWeE1inz2JE&hl=nl&sa=X&ved= …

Re: Unaligned memory access and bus width

Posted on 2018-01-21, 20:48

Just wanted to try running the app(whichcpu) when I noticed a bug causing the disk image to be unreadable by MS-DOS(Wrongly reported default CHS values). After having fixed those, the MS-DOS 6.22 sfdimg/img disk images became unreadable(data 100MB buffer img) and after fixing the CHS formation(using …

Re: Unaligned memory access and bus width

Posted on 2018-01-21, 20:15

It still seems odd to always perform 32-bit accesses or 16-bit accesses. Imagine a 32-bit access on VGA VRAM window edge case(like prefetches) at 9FFFF when reading a byte(valid on protection). It would fetch VRAM as well in your case, even when masking partly off? So 9FFFF-A0003, causing VRAM to be …

Re: Unaligned memory access and bus width

Posted on 2018-01-20, 15:17

I'd assume it'd have to be able to do 8-bit reads/writes. Imagine reading VGA VRAM with 32-bit reads only. That would make it incompatible with all (S)VGA read/write modes. Like mode 1 for moving 4 planes at once using a byte read/write using MOVSB causing the wrong bytes to be latched into memory( …

Re: Unaligned memory access and bus width

Posted on 2018-01-20, 13:43

Those accesses from 6/8 don't make any difference in timings? Either two 32-bit accesses or two 16-bit accesses. It's two accesses either way(with half of each discarded on 32-bits), so no difference in timings? So might as well use 16-bit accesses in that case and not needing to use that …

Re: Unaligned memory access and bus width

Posted on 2018-01-20, 10:49

That's exactly what I thought, reading your first posts: If you do a byte read from VGA VRAM, then the resulting 32-bit access would cause the latches to read the wrong bytes(e.g. addr+3 on an alligned 32-bit address, or address+7 on an unalligned one), thus messing up applications using those. Of …

Re: test386.asm CPU tester

Posted on 2018-01-18, 20:38

Just fixed two more bugs: opcodes 0x84-0x87 had their parameters(modr/m and reg) reversed and opcode 0F0D(Deliberate #UD on 80286+) had parameters it shouldn't have(modr/m and immediate entries). Having fixed those, Wolfenstein 3D ends up with a hanging, corrupted main screen(showing logos and …

Re: Finding bugs in 8086-80386 emulation core?

Posted on 2018-01-07, 20:36

I've just taken a look at https://github.com/id-Software/wolf3d/blob/master/WOLFSRC/ID_VL_A.ASM , which seems to be a part of the open-source release of wolf3d.exe . Oddly enough, the piece of code in the previous post doesn't seem to show up? Does that mean that wolf3d.exe/wolf8086.exe are damaged? …

Re: Finding bugs in 8086-80386 emulation core?

Posted on 2018-01-07, 11:09

Just tried it again(wolf3d.exe) with 80386 (compaq deskpro 386). It seems to cause #GP faults all the time reaching a certain point (16b7:0000fffd)? That's quite strange, as it shouldn't happen normally in real mode, even with HIMEM.SYS loaded(which will load a 0xFFFF limit, so it shouldn't trigger …

Re: test386.asm CPU tester

Posted on 2018-01-05, 14:25

Just found out two little things(checks out without errors on the test386.asm testsuite, errors out on the 80186 testsuite): - BCD instructions(various tests(bcd,mul)) flags. - SHL auxilliary carry flag Although it might just be because of the change in logic between 286+ and older CPUs(186-) for …

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