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Re: Finding bugs in 8086-80386 emulation core?

Posted on 2017-11-06, 15:59

Now all instructions, except for the rotate instructions(RCL,RCR, ROL, ROR) SHOULD be working without problems. Oddly enough, the Windows 95 setup still crashes due to a BOUND instruction that's faulting because it's offset is out of the specified range? I also notice that the offset overflows? Is …

Re: test386.asm CPU tester

Posted on 2017-11-06, 14:07

I've redirected all x86 IMUL instructions(except the GRP opcodes) to the following general function(since it's the same for opcodes 69/6B and 0FAF). I also fixed some stage problems(different execution stages(fetch phase(two subphases fetching r/m), execution phase, result phase)), which were …

Re: test386.asm CPU tester

Posted on 2017-11-05, 18:25

I've tried behaviour like http://www.felixcloutier.com/x86/RCL:RCR:ROL:ROR.html , but whatever I do, it doesn't match the EE dump you've made? This is my current code (SHL/SAL/SHR/SAR already checks out without errors now): 8/16-bit(8086+): byte op_grp2_8(byte cnt, byte varshift) { //word d, …

Re: test386.asm CPU tester

Posted on 2017-11-05, 15:45

This is what I've gotten so far: 16-bit: byte op_grp2_8(byte cnt, byte varshift) { //word d, INLINEREGISTER word s, shift, tempCF, msb; INLINEREGISTER byte numcnt; //word backup; //if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count numcnt = cnt; //Save count! s = oper1b; switch (thereg) …

Re: test386.asm CPU tester

Posted on 2017-11-05, 14:00

Just took a look at the 80386 manual at http://x86.renejeschke.de/ and implemented the wrappings on the counts etc. I've ran the testsuite again and after comparisions with the EE reference I saw the following: SAL1=OK SALi=OK SALr=Flags problems SAR1=OK SARi=OK SARr=OK SHR1=OK SHRi=OK SHRr=Flags …

Re: Finding bugs in 8086-80386 emulation core?

Posted on 2017-11-05, 00:00

Just tried to run "EMM386.EXE NOEMS" as a device driver(after loading HIMEM.SYS successfully). Now it seems to crash and hang somewhere in protected mode? Virtual 8086 mode isn't running, just plain protected mode, jumping to the same starting point and storing CR2? Anyone can tell me what's going …

Re: test386.asm CPU tester

Posted on 2017-11-04, 21:44

Managed to fix the IDIV instructions too now, with all variants (as well as normal DIV) functioning properly: The new and improved x86 (with sign support properly added and working) division algorithms: Overflow check support for determining Division error: /* checkSignedOverflow: Checks if a signed …

Re: test386.asm CPU tester

Posted on 2017-11-04, 14:22

I've managed to improve the under/overflow algorithm to detect better, but somehow your EE log reports #DE when it shouldn't be, according to pure logic? /* checkSignedOverflow: Checks if a signed overflow occurs trying to store the data. unsignedval: The unsigned, positive value calculatedbits: The …

Re: test386.asm CPU tester

Posted on 2017-11-04, 12:22

Just asking: what exactly IS the meaning of the different values that are logged in the EE log? What are the values logged with EAX/EDX and PS values? Is PS simply a direct dump of the lower 16 bits of the EFLAGS register(masked to only contain (un)defined bits)? What about the two sets of EAX/EDX …

Re: test386.asm CPU tester

Posted on 2017-11-03, 20:50

I've improved the overflow detection a bit, but it still doesn't catch all or in some cases seems to catch too many overflows? /* checkSignedOverflow: Checks if a signed overflow occurs trying to store the data. unsignedval: The unsigned, positive value calculatedbits: The amount of bits that's …

Re: test386.asm CPU tester

Posted on 2017-11-03, 19:35

I've improved the DIV/IDIV algorithm a bit. Now the DIV instructions check out correctly. But the IDIV instruction seem to fail somehow? Changes: https://bitbucket.org/superfury/unipcemu/commits/a5a3bc454b3343f4b4d54c48382fa270f471bb10 Although it should improve the signed overflow detection, it …

Re: test386.asm CPU tester

Posted on 2017-11-03, 19:02

Aren't signed/unsigned integer values defined as an IEEE standard, thus never changing? If they were to change, lots of files would simply break due to invalid contents? So it should be assumable that using an union to convert between signed/unsigned variables shouldn't pose a problem?

Re: test386.asm CPU tester

Posted on 2017-11-03, 18:05

I know, but I assume that if the data size is constant(e.g. 64-bit integer, 32-bit integer, 16-bit integer, 8-bit integer), it shouldn't be a problem(e.g. uint_64 to int_64 and vise-versa)? The only thing that effectively changes is the sign bit becoming a negative value of itself, assuming C/C++ …

Re: test386.asm CPU tester

Posted on 2017-11-03, 11:09

I've just looked at the DIV0 interrupt firing: I see some strange stack pushes there(according to Visual Studio debugger): fbf8=original CS before INT0 fbf4=EFLAGS f9f4=CS f9f0=EIP That is a crazy jump between EFLAGS and CS? Edit: It's just the 32-bit extension bit (0x8) being used to shift left 2 …

Re: test386.asm CPU tester

Posted on 2017-11-02, 21:15

Strangely enough, using a simple large file text editor doesn't show to find any div instructions when searching the log for some odd reason? Thinking about the problem, there must be a problem related to the stack somehow. The stages should be as follows(assuming no stack changes): call idivloc(esi …

Re: test386.asm CPU tester

Posted on 2017-11-02, 10:33

@hottobar: I've just tried to single step the DIV0 interrupt that happens at the first DIV instruction of the testsuite. I see it's doing it's stuff with ESI(saving it), calling the printStr function to display the error, modifying the return address, IRET to the return address. Then the RETD at the …

Re: test386.asm CPU tester

Posted on 2017-11-02, 05:42

@peterferrie: So, if I understand this correctly: - If opcodes 69/6B r16 decodes as AX/EAX, then it disassembles as the two-operand version. - If opcodes 69/6B r16 decodes as other registers, then it disassembles as the three-operand version. In both cases, behaviour is as the three-operand version? …

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