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Re: (S)VGA address calculation for latch

From how I understood (and as of this morning's 86Box commit, implemented!) read mode 1, it does 8 pixels one by one, and for each pixel, compares each bit (which is on a separate plane) with the corresponding plane's bit in the color compare register, and if its corresponding bit in the color don't …

Re: (S)VGA address calculation for latch

I think you're the only one who has implemented read mode 1 somewhat correctly, though I notice that VGADOC's VGAREGS.TXT says this: 3CEh index 2 (R/W): Graphics: Color Compare Register bit 0-3 In Read Mode 1 each pixel at the address of the byte read is compared to this color and the corresponding …

(S)VGA address calculation for latch

How do I calculate it correctly? I know that I have to AND it with the mask that depends on GDC register 6 bits 7 and 6, so let's say I have 64k at A000 set, that means I have to do: address &= 0xffff Then, assuming this is not chain 2 or chain 4, I have to do: address <<= 2 But what next? I know I …

Re: Logitech C7 serial mouse power-up sequence

I just got reports back from a person who tested the real mouse for me, and basically, when you set DTR active, the mouse raises DSR (and you get a MSR interrupt from the serial port if the serial port is appropriately configured), and when you set RTS active, the mouse raises CTS (and you get a MSR …

Logitech C7 serial mouse power-up sequence

What exactly does the Logitech C7 serial mouse do on the power-up sequence? I mean, the sequence appears to be, set DTR active, then set RTS active, then wait for something, but for what? 86Box's emulated mouse right starts a timer when that happens, that sends the 0x4D ('M') but Windows 2000 (and …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

The number of wait states introduced by a DRAM refresh can be anything from 0 to 6 cycles (assuming no wait state for the refresh memory access itself). The zero case happens when the bus would otherwise be idle. Other cases depending on when the refresh happens with respect to the adjacent CPU bus …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

So far it appears to run fine, except that the credits have no sound but that's because the emulation of the PIT and the PC speaker leaves a lot to be desired, so it's on my list to be eventually either rewritten or ported from DOSBox where I heard PIT mode 1 (which I presume the credits use) works. …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

OK, fixed the DMA channel 0 so that it only triggeres refresh read when the DMA is programmed to read or write, reenigne's blog says the BIOS takes care of that, and my logging has verified that that indeed happens, so that's one thing settled. However, my other question remains - what's with that …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Also, buffering in non-byte(8088)/word(8086) PIQ prefetches can't be right, especially 20+ bytes at once? The prefetch queue operates correctly, 4 or 6 bytes. It's just that the PCem code (which I started from), calls FETCHADD() (which adds the bytes to the prefetch queue) after the instruction has …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

After fixing some REP stuff, making DMA 0 always call refreshread() even when the channel is otherwise inactive, and fixing the cycles of LODSW and REP LODSW, 8088mph reports 1642 cycles and this seems to work: http://citadel.ringoflightning.net/20181122_044201.png . However I now have two more …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

By trap, I mean INT 1, the single-step trap enabled by the T flag. Do those stop the REP on 808x? I know they do from the later steppings of the 386 onwards, and I know they don't on earlier 386 steppings but it's marked as a defect, and I have no idea what happens on 808x and 286.

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

Yes, but what about prefetch queue writes? Those happen at around 4 cycles per write to prefetch queue, for a maximum of 4 writes on 8088, and 6 on 8086. Though I guess I could refactor the code to do that at REP stop due to either condition met or interrupt. Also, does the 8088 stop REP on TRAP? …

Re: 808x MUL/IMUL/DIV/IDIV/REP cycles/operation

So the CPU loops like: - Start timer period; - Execute instruction (this includes fetching the opcode); - Fill the prefetch queue based on instruction cycles + memory R/W cycles + any accumulated prefetch-induced cycles*; - Take care of memory R/W cycles if any; - End timer period; - Service trap, …

808x MUL/IMUL/DIV/IDIV/REP cycles/operation

I'm currently working on getting 86Box's 808x emulation to at least close to the real thing. Fixed the prefetch queue already (at least enough that the 8088mph credits and Snatch-It now work), and brought the cycles detected by 8088mph to 1637 (not much off from the expected 1678 +/- 10), after …

SB16's MPU-401, and intelligent mode

So I'm working on 86Box's MPU-401 emulation again and I recently fixed it to work like the Windows NT 3.5 driver expects it to. This however, raised a question - what mode does the Sound Blaster 16's MPU-401 start in? Intelligent or UART? Based on the driver's source code in the Windows NT 3.5 DDK, …

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