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Re: x86 Jcc vs address size?

Posted on 2019-02-12, 14:09

As far as I understand, the "effective operand size" controls how the instruction behaves, so CS.D=0, no prefix = 16-bit, CS.D=0, 66 prefix = 32-bit, CS.D=1, no prefix = 32-bit, CS.D=0, 66 prefix = 16-bit. For E8/E9, the effective operand size controls the size of the immediate, which is sign- …

Re: x86 Jcc vs address size?

Posted on 2019-02-10, 03:15

I was using OS/2 Warp 3 as a test case, not 2.0. Makes a good test case for protected mode stuff, as it seems to heavily use mixed 16/32-bit code, call gates, etc. The Am486 manual agrees with the Intel manuals, in which EIP <= EIP + SignExtend(operand) AND FFFFh, if the *operand-size* is 16-bit. It …

Re: x86 Jcc vs address size?

Posted on 2019-02-09, 05:38

Pentium manual says the relative jumps are EIP <= EIP + rel8/rel16/rel32, masked with FFFFh if operand size is 16-bit. Indirect jumps are EIP <= r/m16 or 32 (so zero-extended?), then masked with FFFFh if operand-size is 16-bit. As the address referred to by the pointer will be the same size, AFAICT …

Re: x86 error code size pushed?

Posted on 2019-02-08, 12:41

In my emulator I have it pushing the size corresponding to the gate type (same with the flags/CS:IP). Task switches depend on whether the incoming task is 32-bit or 16-bit. The Intel manuals cover the specifics in some detail if you look at the INT/INTO instruction.

Re: x86 MOV SS invalid?

Posted on 2019-02-03, 02:24

Both depending on whether the segment is present or not. This is pretty clear in the intel manuals, I would trust that over random web pages. if (segment == Segment_SS) { if (reg_value.rpl != GetCPL() || descriptor.dpl != GetCPL() || !descriptor.IsWritableDataSegment()) { RaiseException(Interrupt_ …

Re: Debian/Sandsifter on UniPCemu

Posted on 2018-11-20, 12:53

I couldn't find a disk image with that specific kernel version, so can't check the IP, but FWIW I'm only seeing 0x002B and 0x0018 loaded into FS. The only exception I'm seeing raised during early boot is a page fault for 0xC0000000.

Re: x86 cr2 after page fault?

Posted on 2018-11-16, 02:43

If the value being written into the page directory is invalid, it might be worth setting a memory breakpoint on the physical address of the PDE, and examining the CPU state. If you find the instruction which is setting it, I can compare to my emulator.

Re: 80486 paging protection faults?

Posted on 2018-10-15, 14:20

I'm only seeing one invalid opcode during Win95(A) boot, and quite late in the process, at a different address/instruction bytes: Invalid opcode at EIP = 0117:0000B927h (0x000140C7) EAX=00000283 EBX=00000006 ECX=0000003B EDX=000103B2 ESI=00000004 EDI=00000000 ESP=C13C1FEA EBP=00000000 EFLAGS= …

Re: 80486 paging protection faults?

Posted on 2018-10-13, 04:35

The wording there does seem a bit confusing. As far as I understand, both should raise #PF, regardless of whether it was a present or access issue. Section 9.9.14 would seem to agree with that. (if you think about it, OSes which use page permissions to implement CoW semantics would have to decode …

Re: Accessing CR2/CR3 at CPL 1,2,3?

Posted on 2018-10-13, 04:17

From the Pentium manual: - PMode: #GP(0) if CPL != 0 for all control registers, #GP(0) if writing to reserved bits of CR4 - Real Mode: Interrupt 13 (which is #GP) if writing to reserved bits of CR4 - V8086 Mode: #GP(0) unconditionally Which makes sense, you wouldn't want userspace to be able to …

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