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Re: 3 (+3 more) retro battle stations

Didn't bother with 256Kb. When i was examining these boards the objective was to max-them-out in all ways and see where the boundary is. So it had to be 1Mb level 2 cache buffer. I am sure 256Kb will be more stable, but that's not very interesting (to me at least). Thanks for the photos of the mod. …

Re: 3 (+3 more) retro battle stations

@Feipoa Fixed the original post. I meant level 2 cache, but not level 1. Good catch. As for modifying the Chaintech 486SPM motherboard - during testing i was warm on the idea, but list interest soon after that. That assembly didn't impress, so motivation was not there. Maybe at some point later. --- …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2)

Missed that line. Ok, so you are seeing the same thing. Too bad. The 60/66MHz 3222 1Mb config is actually slower than 256Kb at 2111, which kind of defeats the point. At 50MHz 2111 should be possible with the 1Mb buffer. I can do it here. Feels like unlucky chips you got. In general all chips must be …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (if your only other option is L2 at 3-2-2-2)

several years ago i strapped 1024kb L2 cache on the UUD board. was able to get it to 2111 at 40 and 50 mhz fsb. tried veey hard to achieve the same at 60/66 but without success. only 3222 was fully stable. used trusted chips that do it on SiS based boards, but the UUD guy didnt want to play along. …

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