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Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

Now, that's funny. I had no issues with 2-1-1-1 at 40MHz on the Biostar board and RAM WS 0/0 with the 5x86. I did need 1/0 on RAM WS to get stable operation on the HOT-433 with an earlier 8881 revision, though. This is correct, 2-1-1-1-1, 0ws/0ws, 40 MHz, cx5x86, and 256K is not an issue, even with …

Re: Help wanted --> ALI M1429/M1429G : Need peoples with M1429 board that have a BIOS for adult to dump chipset register

I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits. Great, that should speed the thing up if that work! Thanks I found the following settings: 12 10: Hidden …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

The CY7C1009D has the "classic" pin layout the DIL chips had, but these chips are increasingly hard to find. If you can manage to adopt your PCB-layout to the later pinout (with Vcc pins at the center) sourcing the chips would be far easier in the future. Are you talking about the CY7C1049G for …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

My statement was only to serve as an agreement - ensure the PCB can be used for 1024K double-banked and 512K double-banked, which it seems like you are planning for. Yes, 512K with A19 grounded, pulled to 5V (directly or using a 10K resistor) makes an plug-and-play experience to get to 512K without …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

Yes, I think it would be good if your PCB can be easily adapted to 512K, assuming these 10 ns SOJ chips are still available. I already included the resistor on CPU A19 / Cache A16 / Tag A15 into the design that will become "v1.0". And as I said, it's easily bodged on in the prototype design, and …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

It has been about 8 years since I have looked into this modification. In preparation for this modification, I looked at the convention used on 3 or 4 other motherboards for 1024K. In my MB-8433UUD manual, page 8, which describes the details for this cache mode, I have noted: 4) Solder in a 10K SMD …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

I will be interested to see if this works well. In looking at your board, I don't see the 10K resistor to be used on TAG A15 and A16. Why would you need resistors on the TAG address bits? This board is not meant to be adaptable to different cache sizes, it only works with 9 chips of 128k x 8. So …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

Wouldn't you want to use all the motherboard's female cache sockets to connect to the male pins on the PCB, even if unused, for increasing hold-on strength? It connects into all sockets, but not into all pins.The pins to connect to the sockets are through-hole. The SOJ chips don't fit mechanically …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

feipoa wrote on 2023-04-03, 23:09: How does this PCB connect to the MB-8433UUD? The pins on the "back side" should be IC header pins (round, thinner than displayed) and they plug directly into the cache sockets of the board. All signals and power is taken from the cache sockets, except for A19, …

Re: 486 board with UMC 8881E/8886B: The winner is: EDO without L2 (terms and conditions apply)

What is your source for CY7C1009BN? I don't see this P/N on mouser or digikey. Looking forward to you (eventual) SRAM gadget. That chip has been superseeded by the CY7C1009D. I see it offered for ~3,60€ / piece (at qty 10-100) on Mouser (in stock!) at the 10ns speed grade. While that price is not …

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