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Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

The whole 64MB is cacheable by L2 cache according to ctcm 1.6 (from the german ct magazine, Andreas Stiller) Thank you for letting me know, I wonder why [Cache-0 Latency] works as expected some time and not others. How are you getting on with your other EISA system? BTW I have released 5.46 so you …

Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing

This is because the SB16 is ISA, hence it doesn't support the extended EISA features that would allow identification via this interface. The Non-PnP SB16 version can be detected directly only by testing various I/O locations. Such detection might work more-less in DOS when no other applications/ …

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