Re: SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
Posted on 2022-02-21, 08:34
I've just gone and measured the part and it is indeed a resistor (0 Ohm link)
Re: SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
Posted on 2022-02-21, 08:06
Until I have seen actual proof I am very suspicious of a (capacitor) actually being able to strap cache config bit. You can't use capacitors as pullup/downs for GPIO/Register bit mask strapping. Unless that is not a capacitor, but a resistor disguised as one. I'll be trying this myself on my K6-2+ …
Re: Sram SIMMs
Posted on 2022-01-05, 12:54
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Re: Sram SIMMs
Posted on 2022-01-05, 12:49
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Re: Tyan S1564S to S1564D single to dual processor conversion
Posted on 2021-12-24, 19:42
Just adding this while I'm at it. Here is the 430HX PCISet design Guide document as well. Have fun making your own 430HX board 😂 Merry Christmas everyone.
Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing
Posted on 2021-12-24, 14:36
Thanks for that, much appreciated. Here is the new data including DMI file you requested. I see it also contains a copy of the BIOS region from RAM. It is award 4.50PG and really it predates DMI and many modern features. The BIOS is a custom conversion built from the AOpen DP5 bios, and looking at …
Re: Tyan S1564S to S1564D single to dual processor conversion
Posted on 2021-12-24, 13:04
So you think that I’ll notice the problem there when I go to install a ISA card? Thoughts on why we have discovered no less than three different configurations for those SMDs? Do you think there is a danger in plugging in a isa card with it left as is? How strongly do you recommend matching these …
Re: Tyan S1564S to S1564D single to dual processor conversion
Posted on 2021-12-24, 12:59
Someone suggested using 64mb sticks. The boards are generally designed around a 64MB SIMM per slot maximum, as such half of the boards SIMM slots usually only have half the available RAS lines connected and/or are shared with primary slots. This was a popular design decision back in the day when …
Re: Tyan S1564D to tyan s1564D dual processor conversion
Posted on 2021-12-24, 12:42
Well, I got bored Went ahead and just used the AMP socket. 8E86E56F-50E7-45FB-8153-38D347F48D54.jpeg6A2814C4-338B-4C1E-BF7F-6CFAA559CCA8.jpeg I did notice this: but haven’t done anything about it yet67170689-57EE-4055-8E22-20B3BD17B66A.jpeg92BF016D-3AC8-4C16-91BF-D41CC4DA1D55.jpeg It seems to post …
Re: Tyan S1564S to S1564D single to dual processor conversion
Posted on 2021-12-24, 12:29
Catsay just jumping in here, to say this all looks pretty good. Well done, great job on the dual socket conversion @Sphere478! And about the 430HX/430NX boards, their design is maxed out at 512K of cache and 512MB of ram. While the cache and memory controller could technically support enough address …
Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing
Posted on 2021-12-24, 12:00
Here is another one that may be of interest. Dual 430NX, but I'm getting some odd values reported. 72Mhz FPM/FSB (it is 60Mhz) Timings read as X444/x444 for Read/Write But they are actually X444/X333 Read/Write. Memory detects 128MB in Row 0. However it should be 2 Rows of 64MB each. About, the BIOS …
Re: SIV support for 386/486/586 class + Alpha CPUs and 3dfx + S3 + SiS + Matrox + XGI + old ATI + NVidia GPUs - Testing
Posted on 2021-12-23, 16:44
This is from a SiS552LV Processor. It has 8K of L1i and 8K of L1d. Not all that much is known about these VorteX86 based designs AFAIK it's based on the Rise mP6 and has the 0.18µm Kirin core, please will you try SIV32L on it and post the Menu->File->Save Local file so I can see how SIV does? The …
Re: Need help to improve the support of 486/586/686 class CPUs in CPU-Z
Posted on 2021-12-23, 13:19
Here is a really fun one for you. https://valid.x86.fr/2y4kn2 This is from a SiS552LV Processor It has 8K of L1i and 8K of L1d Not all that much is known about these VorteX86 based designs
Re: Adventures in rebuilding a BIOS for the Sprint P5N-DP V3 (rare dual socket 5 board)
Posted on 2021-12-15, 19:43
Just realized I never actually posted a picture of my custom BIOS for this board. So here you are: Filename 2A59ACAT P5-DP Custom BIOS.jpeg File size 168.53 KiB Views 1339 views
Re: Adventures in rebuilding a BIOS for the Sprint P5N-DP V3 (rare dual socket 5 board)
Posted on 2021-12-13, 15:38
Time for the real stuff! Filename kernel 5.15 booting.png File size 1003.48 KiB Views 1385 views I've gotten the latest Linux Kernel booted and running on this thing. Filename cpuinfo + kernel.png File size 1.08 MiB Views 1385 views So how much storage does your pentium 1 have? Ah yeah a casual 1TB …
Re: Adventures in rebuilding a BIOS for the Sprint P5N-DP V3 (rare dual socket 5 board)
Posted on 2021-12-12, 14:09
After much toil and suffering I have a new update. L2 cache is working again FINALLY!! cpu-z cache functional.png Here is proof of that alongside a quick test of aida64 version 2.50. cpu-z cache test no optimizations.png Now that this is all working I can actually start optimization work alongside …
Re: Adventures in rebuilding a BIOS for the Sprint P5N-DP V3 (rare dual socket 5 board)
Posted on 2021-12-08, 17:11
Next modifications that are about due: - Already modified BIOS for very low AT and PCI clk ratios - Replace all the slow 74 F 244/245/373 series logic chips with ultra fast 74 ABT series. (MOAR MHZ!!!) - Replace the crystal oscillator can driven FSB with a custom PLL PCB and inject any desired FSB …
Re: Adventures in rebuilding a BIOS for the Sprint P5N-DP V3 (rare dual socket 5 board)
Posted on 2021-12-08, 17:02
So as an update. It turned out that the cache I originally though working was a fluke. A bunch of chips and the buffers for them were degraded. A while ago I actually went about testing the cacheless wonder. Well here are some more images. When did you ever see Vintage Edition CPU-z with the Socket …
Re: Dual amd K6 computer
Posted on 2021-12-03, 09:19
Lets put this train to rest. K5/K6/K6-2/K6-2+/K6-3, basically everything prior to AMD's K7 with the DEC licensed EV6 processor bus lacks both the Signalling pins for SMP and the appropriate LAPIC (Local APIC) functionality inside the core to handle dual CPU Interrupt request handling or the ability …
Re: Testing sram with TL866
Posted on 2021-08-27, 07:01
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