VOGONS

Search

Common searches

Search results

Display options

Display options

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-31, 16:19

Why would prefixes taking less EU and BIU cycles for prefixes (proper 2 (1 EU PIQ and 1 prefix parsing) instead of 3(1 EU PIQ and 1 prefix parsing)) return a higher metric cycle in 8088 MPH? Shouldn't it run those instructions faster (less cycles), lowering it instead? Can't say for sure, but a …

Re: MartyPC

Posted on 2023-07-31, 02:15

Will the "device control" debug tool be back in some fashion? Looking through the commits tells me it was considered unstable and hidden behind a 'devtools' build config option. As I seem to recall, it allowed you to step through execution in multiples of PIT/CGA/etc ticks... at least I assumed …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 22:37

Is the immediate being fetched in the instruction itself a common behaviour? Or more of an exception? It complicates disassembly though. It's the behavior of any instruction with a 'rm, imm' form. The decode in general doesn't know about ANY operands that aren't a modrm; it just decodes prefixes, …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 22:18

OK. So if I read it correctly, the fetch from BIU goes until the immediate, then execution starts, which reads it(documented instruction), then it reads the immediate from PIQ instead? Is that what is happening? Edit: I think I've simply misunderstood what you meant with reading the 'EA'. I thought …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 17:36

Isn't that essentially the same? First the TEST opcode is fetched and read (every empty PIQ waiting 1 cycle) in 1 cycle, then the same for the modr/m byte and the remaining modr/m parameters and finally the immediate. It's still the same result? No it is not the same. We're talking about cycle- …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 17:17

It does it in the following order: First read TEST opcode (F6), then rm parameters, then imm(every byte/word/dword parameter so far are in 1-cycle fetches from the prefetch buffer, unless not buffered yet(kept pending for 1 cycle until buffered), thus as per the 8088/8086 documentation afaik (every …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 16:15

So the cycle after the final S state will be when the instruction handling actually starts (when the EU starts 'decoding' etc.). Then the instruction is logged once 'decoding' ends, which is usually the cycle after S, unless some extra timing is applied. Those extra cycles are EA calculations, some …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-16, 14:09

Just a small question: what is the program dumping? Pit clock counts(compared to the reload value)? CPU cycles? Raw pit clock counts read from the PIT registers (after latching)? It sends the latch command and reads timer 0. The timer started at FFFF so you can calculate the elapsed ticks at each …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-14, 20:33

Let me expound a bit. The decode phase of the 8088 will fetch prefixes, the opcode byte itself, and the modrm byte if there is one. That's it. Anything else the instruction needs, like reading the EA operand, reading a displacement, or any immediates, is done by the EU in microcode. The first two …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-14, 20:17

Actually just 5 cycles is impossible. The JMP opcode (opcode EAh) is 5 bytes long, so requires 5x4 cycles to prefetch first. That's exactly what happens in UniPCemu now with the T4 cycle result bugfix I just implemented (using a simply 4-byte fifo buffer for everything the BIU can fetch in one go). …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-14, 19:22

Just modified the 8F opcode as you wrote. 00:00:25:24.08614: BIU T1 00:06:16:98.02016: BIU T2 00:06:16:98.02912: BIU T3 Physical(p):000ffff0=ea(ê); Paged(p):000ffff0=ea(ê); Normal(p):00000000=ea(ê) 00:06:16:98.03168: BIU T4 00:06:16:98.03392: BIU T1 00:06:16:98.03584: BIU T2 00:06:16:98.03776: BIU …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-14, 17:23

Is that 1 cycle before pop for all POPs? What about RETF? UniPCemu does 2 cycles before all POPs. Also, what do you mean with "write operand"? What timing is that (in cycles?)? Also, memory? Reg operand? Nope, just that particular form (8f) Since there is a memory operand, POP rm8/16 has to stash …

Re: UniPCemu 8088 cycle accuracy

Posted on 2023-07-14, 03:15

superfury wrote on 2023-07-14, 02:50: Also, see my edited last message about pop word [cs:bx]. Is 5 idle EU cycles after reading RAM correct, ending at T2 of a possible second prefetch byte? the way i have pop rm16: 1 cycle pop stack (timing from biu) 1 cycle if mem operand,+2 cycles write operand

Page 9 of 15

Go to top of page Go to top of page
Close window
Close window