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Reply 20 of 268, by gerwin

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This evening I added rough Cyrix 5x86 detection to SetMul, thereby making v1.2 acceptable for release. But since I can currently only test it with the PCem emulator, I will not overwrite SetMul v1.1 yet. It is attached here instead.

The parameters for the Cyrix 5x86 are: multiplier 1,2,3,4 and half speed toggle HSE, HSD. But as mentioned in my previous post, not all documented settings have an effect.

EDIT: Deleted SetMul 1.2 download form this post: moved it to 1st post.

Last edited by gerwin on 2016-03-07, 02:43. Edited 1 time in total.

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Reply 21 of 268, by trodas

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Very interesting utility, thanks a lot!

PS. could it get used to enable/disable cache on the run in Win2k/WinXP too...? All I see was:

Intel Architecture manual A.3 indicates that cr0 register can be set to disable cache by setting bit 30, i wrote the above code then :

invd
mov eax,cr0
mov eax,40000000H ;set bit 30
mov cr0,eax

...similar for enabling, but I quess that cache flush must happen first and also that such code will need to run in admin properties, as the slow-down w/o caches is BRUTAL. But... can it be done?

It is dangerous to be right in matters on which the established authorities are wrong. Voltaire
I believe that all the people who stand to profit by a war and who help provoke it should be shot on the first day it starts... Hemingway

Reply 22 of 268, by gerwin

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Here is a simple executable that does just that. It is called CacheOff.exe:
Re: A question about speed
Unfortunately it does not make any difference when testing it on Windows XP. The OS or Protected Mode system does not allow it I suppose.
The normal way to do direct hardware calls in an NT OS is to install a driver to do that, or register a driver process in runtime.

Something else: Yesterday I tested SetMul v1.2 on a real Cyrix 5x86. It still works as expected. 😀 CPU Detection works, and it can switch between the startup multiplier and 1x and back.
Some additional functions do not work, despite following the datasheet by the letter: multiplier readout, half-speed, third multiplier option. Regardless, I will leave these options in the program for now.

--> ISA Soundcard Overview // Doom MBF 2.04 // SetMul

Reply 23 of 268, by Jolaes76

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Thanks for the effort to expand the scope of this great little utility!

Even without the half-speed etc. functions, it is now possible to slow an Cx5x86 to a mid-range 286 by disabling L1/L2 caches and dropping the multiplier to 1x. The rest (masquerade physical RAM size, XMS amount, VGA speed throttling) is a lesser challenge 😀

"Ita in vita ut in lusu alae pessima iactura arte corrigenda est."

Reply 24 of 268, by j^aws

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gerwin wrote:
... The next and final C3 version behaves differently, it makes the previous versions seem unfinished. Cache and memory throughp […]
Show full quote

...
The next and final C3 version behaves differently, it makes the previous versions seem unfinished. Cache and memory throughput are sufficient now:
VIA C3 Nehemiah (C5XL) at 9.0x133=1200MHz:
-Speedsys=793,93 pts.
-Quake I - 640x480=71,5 FPS.
-PC Player Bench=106,4 FPS.
This version is not as good in 486 emulation though; It does up to a 486DX-40 at most. Still it does better in that regard then the Intel Pentium II/IIIs.
...

BTW, thanks for maintaining Setmul; very nice utility.

I've been trying out Setmul 1.1 on an Ezra, using a 440BX board, and it's very flexible. I've been running it from 150MHz to 1000MHz. This system scales smoothly from a fast 286 to a fast K6-III+ by using various parameters. I really like the Instruction Cache Disabling (ICD). Just using this option gives me a smooth range from a 486DX-33 to a 486DX2-80.

I was thinking of trying out a Nehemiah, but your aforementioned comments put me off regarding flexibility. Does the ICD option give similar results to what I got with an Ezra, or is the 486DX-40 the limit for a Nehemiah?

Reply 25 of 268, by gerwin

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j^aws wrote:

I've been trying out Setmul 1.1 on an Ezra, using a 440BX board, and it's very flexible. I've been running it from 150MHz to 1000MHz. This system scales smoothly from a fast 286 to a fast K6-III+ by using various parameters. I really like the Instruction Cache Disabling (ICD). Just using this option gives me a smooth range from a 486DX-33 to a 486DX2-80.

Yes it is a very flexible CPU for that purpose, and ICD is indeed key to emulate these 486's. Glad you can second that.

j^aws wrote:

I was thinking of trying out a Nehemiah, but your aforementioned comments put me off regarding flexibility. Does the ICD option give similar results to what I got with an Ezra, or is the 486DX-40 the limit for a Nehemiah?

This is basically it for the Nehemiah slowdown options. I tried everything, including ICD toggle:

Just checked the VIA C3 Nehemiah with the SetMul options for Cache and such, and setting FSB speeds from 50 to 133MHz. Lowest SpeedSys score I could get is 3,77 points (~386SX-20), this could be ramped up gradually to 14,46 points (~486DX-40). When enabling all L1 cache again it jumps to 127,30 points at least.
I could also use Throttle to get even lower Speedsys scores on that machine. But that ACPI slowdown method does not always work well with games.

The Nehemiah is much more like an intel coppermine CPU: Solid performance at the default settings, but heavy reliance on its L1 cache. So it suffers more when L1 cache is disabled: going straight to 386 slowness, just like intel. The only saving grace is that Nehemiah can still disable L1 "I-cache" individually, and thereby emulate a 486DX-40.

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Reply 26 of 268, by PhilsComputerLab

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I would also like to extend my appreciations!

The Exclusively disable L1 cache is really unique. I don't think I was ever able to just change L1 cache on a mobile K6 before. It gives you that tiny bit of extra control if you wish for it 😀

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Reply 27 of 268, by j^aws

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gerwin wrote:

This is basically it for the Nehemiah slowdown options. I tried everything, including ICD toggle:

Just checked the VIA C3 Nehemiah with the SetMul options for Cache and such, and setting FSB speeds from 50 to 133MHz. Lowest SpeedSys score I could get is 3,77 points (~386SX-20), this could be ramped up gradually to 14,46 points (~486DX-40). When enabling all L1 cache again it jumps to 127,30 points at least.
I could also use Throttle to get even lower Speedsys scores on that machine. But that ACPI slowdown method does not always work well with games.

The Nehemiah is much more like an intel coppermine CPU: Solid performance at the default settings, but heavy reliance on its L1 cache. So it suffers more when L1 cache is disabled: going straight to 386 slowness, just like intel. The only saving grace is that Nehemiah can still disable L1 "I-cache" individually, and thereby emulate a 486DX-40.

Thanks for the clarification. One thing that I use to compare equivalent 486 speeds for comparison is NSSI, and this usually has discrepancies with Speedsys. Just to compare your Nehemiah Speedsys scores to my Ezra scores using Speedsys:

Using FSB 50-133MHz, and multi fom 3-7.5:

Speedsys: 78.91 <-> 527.35

w/ ICD:

Speedsys: 17.29 <-> 51.84

w/ L1D, L2D, BPD:

Speedsys: 7.72 <-> 24.61

Really nice speed ranges. Using ICD even prevents Ultima 7 from re-enabling L1 Cache, and works at the appropriate speed. The Ezra is even detected as a Pentium, e.g. Magic Carpet is a speed sensitive game and sees it as a Pentium CPU, and works at the appropriate speed too.

Reply 28 of 268, by trodas

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Makes me wonder - do the multiplier settings that works for the Cyrix 5x86 CPU work also for the Cyrix 6x86 CPU? These PR-166 CPU's aren't bad, but I would love to see them run with x1 multiplier.

Anyone can try this...?

It is dangerous to be right in matters on which the established authorities are wrong. Voltaire
I believe that all the people who stand to profit by a war and who help provoke it should be shot on the first day it starts... Hemingway

Reply 30 of 268, by trodas

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I just naively and blindly hoped, that the 6x86 could happen to be compatible with previous 5x86... So someone tried that already and it did not worked? And there is no good sources for Cyrix advanced docs? I mean... it is interesting, that for 5x86 they are, but not for 6x86... Sadly my board support only 6x86 🙁

It is dangerous to be right in matters on which the established authorities are wrong. Voltaire
I believe that all the people who stand to profit by a war and who help provoke it should be shot on the first day it starts... Hemingway

Reply 31 of 268, by j^aws

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^^ It was discussed in this thread:

Re: Which Socket 3 CPUs can you downclock using 1x multiplier?

Nothing found to suggest Multi can be changed via register settings - only jumper signals.

Reply 32 of 268, by feipoa

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gerwin wrote:

I have modified SetMul to tinker with the multiplier options which are mentioned in the 5x86 Datasheet. The good news is that one can toggle between the bootup multiplier and 1.0x anytime, but seemingly that is about all it can do. It won't do any switching between 2.0x, 3.0x or 4.0x. There is no observed effect of the half clock speed bit.

I beleive you need a 4x-capable Cyrix 5x86 chip to be able to switch from 4x to 2x to 1x, and back to 4x. I will experiment with this the next time I pull out my Cyrix 5x86-133/4x system.

Plan your life wisely, you'll be dead before you know it.

Reply 33 of 268, by feipoa

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I have confirmed that SETMUL correctly sets the multiplier, in any order, between 1x, 2x, and 4x on Cyrix 4x-capable CPUs. I have used CHKCPU to confirm the internal CPU speed. Note that CHKCPU incorrectly displays the multiplier and FSB after using SETMUL or the Evergreen utility to change the clock speed. This is so much easier to use than the Evergreen utility. Much appreciation for adding the Cyrix 5x86 to the list of supported CPUs for SETMUL. Now will the Cyrix Media GX work...?

Vetz: Did you implement half-clock with SETMUL? If so, how is it toggled. I think it will be difficult to determine if half-clock is functioning because once you run a program to check for the internal clock speed, it goes out of half-clock mode.

Plan your life wisely, you'll be dead before you know it.

Reply 34 of 268, by gerwin

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Vetz? you mean me right?

Thanks for checking. Glad it can toggle three multipliers on that CPU. Though I notice 3x mode was not listed in your post.

Current Multiplier readout is not working: despite reading the registers stated in the 5x86 datasheet. Since the hardware is not communicating the proper value, mine and other people's software won't display the proper value.

I Suppose you could check half clock mode with a benchmark. Though I don't know what you mean with it going out of half clock mode. Anyway, it did not do anything for me. Half clock speed seems to be a myth, just like multiplier readout.

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Reply 35 of 268, by feipoa

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gerwin, yes I was refering to you. Don't know how the Vetz got in there - I was probably viewing multiple threads.

3x was deliberatly not listed in my post.

A 4x-capable Cyrix 5x86 chip, when booted in 4x mode, can only switch between 1x, 2x, and 4x, not 3x.

A 4x- or 3x-capable Cyrix 5x86 chip when booted in 3x mode, can only switch between 3x and 1x.

A 3x-capable Cyrix 5x86 chip when booted in 2x mode, can only switch between 2x and 1x.

gerwin wrote:

Since the hardware is not communicating the proper value, mine and other people's software won't display the proper value.

Is the improper value repeatable and unique for 1x, 2x, 3x, and 4x? If so, can use these static improper values as a calibration means to display the proper multiplier values?

gerwin wrote:

I Suppose you could check half clock mode with a benchmark. Though I don't know what you mean with it going out of half clock mode. Anyway, it did not do anything for me. Half clock speed seems to be a myth, just like multiplier readout.

When HLF_CLK is set, the internal CPU frequency will run at half the FSB, but only when the bus is idle. When a bus transfer occurs, the CPU frequency shoots up to the frequency from the time before you set HLF_CLK. When the bus transfer has completed, the CPU frequency will go back to half the bus frequency. When running a benchmark, an external bus tranfer takes place because the benchmark is being loaded from the HDD. During the benchmark, data will continue to be read from either HDD, L2 cache, or memory such that the internal CPU speed stays high. If a very small benchmark app. is run which resides entirely in L1 cache, perhaps the internal CPU frequency stay at HLF_CLK? Did you remove the ability to set HLF_CLK from your SETMUL program? Can you reimplement it? Using the Evergreen utility to set HLF_CLK requires more brain power!

Plan your life wisely, you'll be dead before you know it.

Reply 36 of 268, by gerwin

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feipoa wrote:

Is the improper value repeatable and unique for 1x, 2x, 3x, and 4x? If so, can use these static improper values as a calibration means to display the proper multiplier values?

IIRC the received value is always the same.
Maybe there is another means of getting that info? Though I rather not write code to measure the approx CPU speed with a benchmark, then measure the approx FSB with another benchmark. etc.

feipoa wrote:

When HLF_CLK is set, the internal CPU frequency will run at half the FSB, but only when the bus is idle. When a bus transfer occurs, the CPU frequency shoots up to the frequency from the time before you set HLF_CLK. ...... Did you remove the ability to set HLF_CLK from your SETMUL program? Can you reimplement it? Using the Evergreen utility to set HLF_CLK requires more brain power!

OK that makes sense. So it is really aimed at idle power usage. The HLF_CLK functionality is currently there in SetMul.

--> ISA Soundcard Overview // Doom MBF 2.04 // SetMul

Reply 37 of 268, by feipoa

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How do I set HLF_CLK in SETMUL? Would it be,

setmul 0.5

?

Also, have you thought about adding the Cyrix MediaGX to Setmul? There's quite a bit of documentation on th at chip.

Plan your life wisely, you'll be dead before you know it.

Reply 38 of 268, by gerwin

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No, Use "HSE" for half-speed enable, "HSD" to disable. SetMul lists these commands when you run it without parameters, or by passing "/?".

Will check the MediaGX docs. Unfortunately I don't have such hardware myself.

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Reply 39 of 268, by feipoa

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Fortunately, I have a cased MediaGX system to test with 😀

These are the MediaGX docs I have been able to find,
Cyrix MediaGX Data Book - 304 pgs
Cyrix MediaGX Data Book Addendum - 13 pgs
National MediaGXm Data Book - 244 pgs

For whatever reason, my L1 cache is listed as being in write-through mode, which means I need to find a way to toggle the NW bit of the CR0 register (and possibly Lock_NW of CCR2).

Plan your life wisely, you'll be dead before you know it.