Great Hierophant wrote:I would like to know how this slowdown timing works. Could it be lowering the frontside bus from 66MHz to 8Mhz?
Yes. (see below)
Great Hierophant wrote:The frontside bus affects the timing for all other components in the system. The CPU multiplies the bus speed, the RAM, northbridge and southbridge chips run at the bus speed, the PCI bus at half the bus speed and the ISA bus at an eighth of the bus speed. I don't think its that simple, because the RAM and the PCI cards may fail at such low speeds.
Your observation is correct for most modern chipset and board designs.
Since the time when CPUs got faster than the ISA bus, multiple clock speeds were needed for the different components.
There are two ways to get them matching within-specs:
1) Use an oscillator at a certain clock speed and multiply it x times to get the frequencies needed. This is the simplest solution, it's cheap to implement, and works stable up to very high frequencies. The drawbacks are that you don't always get the desired clock speed for a certain component, and unless you implement configurable multipiers (or dividers), some components may run out of spec.
2) Use a clock generator for each device that has to run at a different speeds. The advantage is that you have more flexibility, but you need more sophisticated bridge logic between the components, which is more expensive and not as efficient.
Most boards use a mix of both methods. So the Dell PC (and many others) have the buses running independent from the CPU clock and can be adjusted accordingly. My 486 board has CPU and PCI/VESA bus speeds linked, but can run the ISA bus from an extra 8 MHz clock generator. It always depends on the board design.
