Trying to find information on how NMI is invoked. Below would be what to do once triggered, but how/where to trigger..
I put this in cpu.cpp, check in normal_loop.
bool CPU_NMI=false;bool CPU_NMI_Check(void) {if (CPU_NMI) { // && RealGetVec(0x02)) {CPU_SW_Interrupt(2,reg_eip-SegPhys(cs)); // GetIP());CPU_NMI=false;return true;}return false;}
NMI should be a hw interrupt, better put it into PIC_RunQueue like the regular irq's.
Triggering is through the NMI line of the cpu, i only know it was used to
signal memory errors (parity check failure) to basically halt the pc.
ISA cards can cause a NMI through the IOCHCK bus line.
1+1=10
Yes, I understand the physical connection, that the cpu has two IRQ pins, one hooked up to the PIC, the other the NMI. I also considered sticking it in into the PIC, but didn't think you guys would be interested in a hack-esk implementation. The source for the interwave sbos version is even available, http://alsa.cybermirror.org/datasheets/gus/amd960214.tar.gz, yet I've managed to miss how they're invoking it(look at loader.c, setup_nmi(), test_nmi(), and search for nmi in general). I see them enabling NMIs, installing their test nmi handler for INT 2, but miss how they're triggering the NMI for their nmi count to increment. Interstingly enough, at one time the source for the original GUS/MAX was available but has unfortunately since gone MIA. In case you're wondering why bother, when it worked, SBOS would often sound better than OPL playback, ultrabots being an example; sounding cool instead of dinky.
Actually pic would be wrong, as it can be triggered at instruction boundaries.
How it might work:
In void enable_nmi_irq(void) the gus is setup to trigger an NMI when a game later reads or writes to the Adlib/MPU registers.
1+1=10