First post, by Heathen
Hi all,
First, apologies as I've read through a bunch of threads that touch on this topic here so I know it's been discussed at least in passing a few times, albeit with slightly contradictory steers.
I have a Jetway 542B motherboard that I'm about to assemble alongside a K6-2 500 and 128MB of SDRAM. I'd initially read that bugs in that board's Aladdin V M1542 chipset mean that only 128MB of RAM can be cached without a performance penalty that may outweigh any increase in RAM (something to do with the TAG RAM implementation?) I've then seen conflicting advice across the years on this board about whether this was resolved in some board revisions, whether this is isolated only to those K6 chips without onboard L2 (i.e. pre 2/3+ CPUs) and how meaningful the impact really is.
I wanted to ask:
- Is this problem genuine (i.e. if I were to add more SDRAM to this system, all else being equal, would the problem manifest) and how significant is the performance penalty?
- Is it true that this issue would be resolved if the K6-2 were to be replaced by a 2/3+ with onboard L2 cache?
- Are there other options to address the issue? I understand it's not a BIOS problem so not something a later or patched BIOS can address. Is this issue widespread for SS7 systems or isolated to Aladdin V chipsets?
- I've seen some scattered references to certain SS7 boards suffering significant performance penalties swapping in 2/3+ CPUs, again possibly at a hardware level. Is this something I need to be aware of for this chipset/board? I'd obviously like to avoid swapping one problem for another!
Regards,
Greg