VOGONS


Reply 60 of 110, by feipoa

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TheMobRules, do you have the version of the P/I-P55TP4XE (I think rev. 2.4) which has JP16 installed? See image below.

If your board has JP16, could you remove the jumper and trace out where the 3 jumper pins go?

Also, if your board is able to be run without too much of a fuss, could you run CTCHIP34 as:

C:\CTCHIP34\CTCHIP34.exe intelpci.cfg

Press Page Down 13 times, and you'll be at register 52h. Press the percent button % and you will have access to adjust the 8 bits in the register. But before you adjust them, what values are presented? I am guessing you will see 01000001.

If you adjust this value to 00000000 by pressing ENTER, exit, run some game or whatever to ensure system still works, then go back into CTCHIP34 and adjust this again to 01000001, exit, can you still run DOOM or whatever app?

What if you adjust this value to 00100011, exit, then adjust it back to 01000001, can you still run your applications?

Ultimate 486 Benchmark | Ultimate 686 Benchmark | Cyrix 5x86 Enhancements | 486 Overkill Graphics | Worlds Fastest 486

Reply 61 of 110, by rasz_pl

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GOT IT

_F000:E1F4                 mov     cx, 52h ; 'R'
_F000:E1F7 mov al, 0A2h ; 'ó'
_F000:E1F9 mov sp, 0E1FFh
_F000:E1FC jmp pci_write_dev

Bios never reads initial 52h value. We start by turning on _512 Kbytes Asynchronous_ and testing that, reading on to see if it ever tries PB

whole thing:

_F000:E0B6 ram_cache       proc near               ; CODE XREF: _F000:E4F0j
_F000:E0B6 shl esp, 10h
_F000:E0BA mov cx, 61h ; 'a'
_F000:E0BD mov al, 32h ; '2'
_F000:E0BF
_F000:E0BF loc_FE0BF: ; CODE XREF: ram_cache+15j
_F000:E0BF mov sp, 0E0C5h
_F000:E0C2 jmp pci_write_dev
_F000:E0C2 ; ---------------------------------------------------------------------------
_F000:E0C5 dw offset loc_FE0C7
_F000:E0C7 ; ---------------------------------------------------------------------------
_F000:E0C7
_F000:E0C7 loc_FE0C7: ; DATA XREF: ram_cache+Fo
_F000:E0C7 inc cx
_F000:E0C8 cmp cx, 64h ; 'd'
_F000:E0CB jbe short loc_FE0BF
_F000:E0CD mov ax, cs
_F000:E0CF mov ds, ax
_F000:E0D1 assume ds:_F000
_F000:E0D1 lea di, unk_FE090
_F000:E0D5 lgdt fword ptr [di]
_F000:E0D8 mov eax, cr0
_F000:E0DB or al, 1 ; Switching to Protected
_F000:E0DD mov cr0, eax
_F000:E0E0 jmp short $+2
_F000:E0E2 mov cx, 18h
_F000:E0E5 mov ds, cx
_F000:E0E7 assume ds:nothing
_F000:E0E7 mov cx, 61h ; 'a'
_F000:E0EA xor edi, edi
_F000:E0ED mov al, 0
_F000:E0EF
_F000:E0EF loc_FE0EF: ; CODE XREF: ram_cache+99j
_F000:E0EF mov word ptr [edi+800000h], 0AA55h
_F000:E0F8 mov word ptr [edi+1000000h], 0AA55h
_F000:E101 mov word ptr [edi], 55AAh
_F000:E106 mov word ptr [edi+4], 0AA55h
_F000:E10C cmp word ptr [edi], 55AAh
_F000:E111 jnz short loc_FE137
_F000:E113 cmp word ptr [edi+4], 0AA55h
_F000:E119 jnz short loc_FE137
_F000:E11B add al, 2
_F000:E11D cmp word ptr [edi+800000h], 55AAh
_F000:E126 jz short loc_FE137
_F000:E128 add al, 2
_F000:E12A cmp word ptr [edi+1000000h], 55AAh
_F000:E133 jz short loc_FE137
_F000:E135 add al, 4
_F000:E137
_F000:E137 loc_FE137: ; CODE XREF: ram_cache+5Bj
_F000:E137 ; ram_cache+63j ...
_F000:E137 mov sp, 0E13Dh
_F000:E13A jmp pci_write_dev
_F000:E13A ; ---------------------------------------------------------------------------
_F000:E13D dw offset loc_FE13F
_F000:E13F ; ---------------------------------------------------------------------------
_F000:E13F
_F000:E13F loc_FE13F: ; DATA XREF: ram_cache+87o
_F000:E13F xor edx, edx
_F000:E142 mov dl, al
Show last 388 lines
_F000:E144                 shl     edx, 16h
_F000:E148 mov edi, edx
_F000:E14B inc cx
_F000:E14C cmp cx, 64h ; 'd'
_F000:E14F jbe short loc_FE0EF
_F000:E151 mov cx, 58h ; 'X'
_F000:E154 mov al, 8
_F000:E156 mov sp, 0E15Ch
_F000:E159 jmp pci_write_dev
_F000:E159 ; ---------------------------------------------------------------------------
_F000:E15C dw offset loc_FE15E
_F000:E15E ; ---------------------------------------------------------------------------
_F000:E15E
_F000:E15E loc_FE15E: ; DATA XREF: ram_cache+A6o
_F000:E15E mov al, 1Fh
_F000:E160 mov cx, 68h ; 'h'
_F000:E163 mov sp, 0E169h
_F000:E166 jmp pci_write_dev
_F000:E166 ; ---------------------------------------------------------------------------
_F000:E169 dw offset loc_FE16B
_F000:E16B ; ---------------------------------------------------------------------------
_F000:E16B
_F000:E16B loc_FE16B: ; DATA XREF: ram_cache+B3o
_F000:E16B mov al, 9
_F000:E16D mov cx, 57h ; 'W'
_F000:E170 mov sp, 0E176h
_F000:E173 jmp pci_write_dev
_F000:E173 ; ---------------------------------------------------------------------------
_F000:E176 dw offset loc_FE178
_F000:E178 ; ---------------------------------------------------------------------------
_F000:E178
_F000:E178 loc_FE178: ; DATA XREF: ram_cache+C0o
_F000:E178 mov bl, 1Eh
_F000:E17A mov cx, 60h ; '`'
_F000:E17D xor edi, edi
_F000:E180
_F000:E180 loc_FE180: ; CODE XREF: ram_cache+10Bj
_F000:E180 inc cx
_F000:E181 cmp cx, 64h ; 'd'
_F000:E184 ja short loc_FE1C3
_F000:E186 mov sp, 0E18Ch
_F000:E189 jmp pci_read_dev
_F000:E189 ; ---------------------------------------------------------------------------
_F000:E18C dw offset loc_FE18E
_F000:E18E ; ---------------------------------------------------------------------------
_F000:E18E
_F000:E18E loc_FE18E: ; DATA XREF: ram_cache+D6o
_F000:E18E xor edx, edx
_F000:E191 mov dl, al
_F000:E193 shl edx, 16h
_F000:E197 cmp edi, edx
_F000:E19A jz short loc_FE1AF
_F000:E19C mov dword ptr [edi], 0FFFFFFFFh
_F000:E1A4 cmp dword ptr [edi], 0FFFFFFFFh
_F000:E1A9 jz short loc_FE1BE
_F000:E1AB xor bl, bl
_F000:E1AD jmp short loc_FE1C3
_F000:E1AF ; ---------------------------------------------------------------------------
_F000:E1AF
_F000:E1AF loc_FE1AF: ; CODE XREF: ram_cache+E4j
_F000:E1AF mov ah, cl
_F000:E1B1 mov al, 1
_F000:E1B3 and cl, 7
_F000:E1B6 shl al, cl
_F000:E1B8 not al
_F000:E1BA and bl, al
_F000:E1BC mov cl, ah
_F000:E1BE
_F000:E1BE loc_FE1BE: ; CODE XREF: ram_cache+F3j
_F000:E1BE mov edi, edx
_F000:E1C1 jmp short loc_FE180
_F000:E1C3 ; ---------------------------------------------------------------------------
_F000:E1C3
_F000:E1C3 loc_FE1C3: ; CODE XREF: ram_cache+CEj
_F000:E1C3 ; ram_cache+F7j
_F000:E1C3 mov al, bl
_F000:E1C5 mov cx, 68h ; 'h'
_F000:E1C8 mov sp, 0E1CEh
_F000:E1CB jmp pci_write_dev
_F000:E1CB ; ---------------------------------------------------------------------------
_F000:E1CE dw offset loc_FE1D0
_F000:E1D0 ; ---------------------------------------------------------------------------
_F000:E1D0
_F000:E1D0 loc_FE1D0: ; DATA XREF: ram_cache+118o
_F000:E1D0 mov al, 1
_F000:E1D2 mov cx, 57h ; 'W'
_F000:E1D5 mov sp, 0E1DBh
_F000:E1D8 jmp pci_write_dev
_F000:E1D8 ; ---------------------------------------------------------------------------
_F000:E1DB dw offset torealmode
_F000:E1DD ; ---------------------------------------------------------------------------
_F000:E1DD
_F000:E1DD torealmode: ; DATA XREF: ram_cache+125o
_F000:E1DD mov eax, cr0
_F000:E1E0 and al, 0FEh
_F000:E1E2 mov cr0, eax
_F000:E1E5 jmp far ptr loc_FE1EA
_F000:E1EA
_F000:E1EA loc_FE1EA:
_F000:E1EA mov al, 0FFh
_F000:E1EC mov sp, 0E1F2h
_F000:E1EF jmp CMOS_L1cache
_F000:E1EF ; ---------------------------------------------------------------------------
_F000:E1F2 dw offset cache_detect
_F000:E1F4 ; ---------------------------------------------------------------------------
_F000:E1F4
_F000:E1F4 cache_detect: ; DATA XREF: ram_cache+13Co
_F000:E1F4 mov cx, 52h ; 'R'
_F000:E1F7 mov al, 0A2h ; 'ó' ; 512KB Async Normal L2 cache operation (dependent on SGS)
_F000:E1F9 mov sp, 0E1FFh
_F000:E1FC jmp pci_write_dev
_F000:E1FC ; ---------------------------------------------------------------------------
_F000:E1FF dw offset cache_prefill
_F000:E201 ; ---------------------------------------------------------------------------
_F000:E201
_F000:E201 cache_prefill: ; DATA XREF: ram_cache+149o
_F000:E201 cld
_F000:E202 mov dx, 8000h
_F000:E205
_F000:E205 loc_FE205: ; CODE XREF: ram_cache+15Dj
_F000:E205 mov ds, dx
_F000:E207 assume ds:nothing
_F000:E207 xor si, si
_F000:E209 mov cx, 4000h
_F000:E20C rep lodsd
_F000:E20F sub dx, 1000h
_F000:E213 jnz short loc_FE205
_F000:E215 mov cx, 52h ; 'R'
_F000:E218 mov al, 61h ; 'a' ; 256KB Async Disabled; tag invalidate on reads
_F000:E21A mov sp, 0E220h
_F000:E21D jmp pci_write_dev
_F000:E21D ; ---------------------------------------------------------------------------
_F000:E220 dw offset loc_FE222
_F000:E222 ; ---------------------------------------------------------------------------
_F000:E222
_F000:E222 loc_FE222: ; DATA XREF: ram_cache+16Ao
_F000:E222 mov sp, 0E228h
_F000:E225 jmp cache_test
_F000:E225 ; ---------------------------------------------------------------------------
_F000:E228 dw offset loc_FE22A
_F000:E22A ; ---------------------------------------------------------------------------
_F000:E22A
_F000:E22A loc_FE22A: ; DATA XREF: ram_cache+172o
_F000:E22A jnb short loc_FE26A
_F000:E22C mov cx, 52h ; 'R'
_F000:E22F mov al, 0B1h ; '¦' ; 512KB PB Disabled; tag invalidate on reads
_F000:E231 mov sp, 0E237h
_F000:E234 jmp pci_write_dev
_F000:E234 ; ---------------------------------------------------------------------------
_F000:E237 dw offset loc_FE239
_F000:E239 ; ---------------------------------------------------------------------------
_F000:E239
_F000:E239 loc_FE239: ; DATA XREF: ram_cache+181o
_F000:E239 mov sp, 0E23Fh
_F000:E23C jmp cache_test
_F000:E23C ; ---------------------------------------------------------------------------
_F000:E23F dw offset loc_FE241
_F000:E241 ; ---------------------------------------------------------------------------
_F000:E241
_F000:E241 loc_FE241: ; DATA XREF: ram_cache+189o
_F000:E241 jnb short loc_FE296
_F000:E243 mov cx, 52h ; 'R'
_F000:E246 mov al, 51h ; 'Q' ; 256KB Burst Disabled; tag invalidate on reads
_F000:E248 mov sp, 0E24Eh
_F000:E24B jmp pci_write_dev
_F000:E24B ; ---------------------------------------------------------------------------
_F000:E24E dw offset loc_FE250
_F000:E250 ; ---------------------------------------------------------------------------
_F000:E250
_F000:E250 loc_FE250: ; DATA XREF: ram_cache+198o
_F000:E250 mov sp, 0E256h
_F000:E253 jmp cache_test
_F000:E253 ; ---------------------------------------------------------------------------
_F000:E256 dw offset loc_FE258
_F000:E258 ; ---------------------------------------------------------------------------
_F000:E258
_F000:E258 loc_FE258: ; DATA XREF: ram_cache+1A0o
_F000:E258 jnb short loc_FE296
_F000:E25A
_F000:E25A loc_FE25A: ; CODE XREF: ram_cache:loc_FE27Fj
_F000:E25A mov cx, 52h ; 'R'
_F000:E25D mov al, 22h ; '"' ; 0KB Async Normal L2 cache operation (dependent on SGS)
_F000:E25F mov sp, 0E265h
_F000:E262 jmp pci_write_dev
_F000:E262 ; ---------------------------------------------------------------------------
_F000:E265 dw offset loc_FE267
_F000:E267 ; ---------------------------------------------------------------------------
_F000:E267
_F000:E267 loc_FE267: ; DATA XREF: ram_cache+1AFo
_F000:E267 jmp loc_FE30E
_F000:E26A ; ---------------------------------------------------------------------------
_F000:E26A
_F000:E26A loc_FE26A: ; CODE XREF: ram_cache:loc_FE22Aj
_F000:E26A mov cx, 52h ; 'R'
_F000:E26D mov al, 41h ; 'A' ; 256KB PB Disabled; tag invalidate on read
_F000:E26F mov sp, 0E275h
_F000:E272 jmp pci_write_dev
_F000:E272 ; ---------------------------------------------------------------------------
_F000:E275 dw offset loc_FE277
_F000:E277 ; ---------------------------------------------------------------------------
_F000:E277
_F000:E277 loc_FE277: ; DATA XREF: ram_cache+1BFo
_F000:E277 mov sp, 0E27Dh
_F000:E27A jmp cache_test
_F000:E27A ; ---------------------------------------------------------------------------
_F000:E27D dw offset loc_FE27F
_F000:E27F ; ---------------------------------------------------------------------------
_F000:E27F
_F000:E27F loc_FE27F: ; DATA XREF: ram_cache+1C7o
_F000:E27F jnb short loc_FE25A
_F000:E281 mov cx, 52h ; 'R'
_F000:E284 mov al, 61h ; 'a' ; 256KB Async Disabled; tag invalidate on read
_F000:E286 mov sp, 0E28Ch
_F000:E289 jmp pci_write_dev
_F000:E289 ; ---------------------------------------------------------------------------
_F000:E28C dw offset loc_FE28E
_F000:E28E ; ---------------------------------------------------------------------------
_F000:E28E
_F000:E28E loc_FE28E: ; DATA XREF: ram_cache+1D6o
_F000:E28E mov sp, 0E294h
_F000:E291 jmp cache_test
_F000:E291 ; ---------------------------------------------------------------------------
_F000:E294 dw offset loc_FE296
_F000:E296 ; ---------------------------------------------------------------------------
_F000:E296
_F000:E296 loc_FE296: ; CODE XREF: ram_cache:loc_FE241j
_F000:E296 ; ram_cache:loc_FE258j
_F000:E296 ; DATA XREF: ...
_F000:E296 mov cx, 52h ; 'R'
_F000:E299 mov sp, 0E29Fh
_F000:E29C jmp pci_read_dev
_F000:E29C ; ---------------------------------------------------------------------------
_F000:E29F dw offset loc_FE2A1
_F000:E2A1 ; ---------------------------------------------------------------------------
_F000:E2A1
_F000:E2A1 loc_FE2A1: ; DATA XREF: ram_cache+1E9o
_F000:E2A1 and al, 3Fh
_F000:E2A3 or al, 80h ; set 512KB, leave type and mode as is
_F000:E2A5 mov sp, 0E2ABh
_F000:E2A8 jmp pci_write_dev
_F000:E2A8 ; ---------------------------------------------------------------------------
_F000:E2AB dw offset loc_FE2AD
_F000:E2AD ; ---------------------------------------------------------------------------
_F000:E2AD
_F000:E2AD loc_FE2AD: ; DATA XREF: ram_cache+1F5o
_F000:E2AD xor si, si
_F000:E2AF xor ax, ax
_F000:E2B1 mov ds, ax
_F000:E2B3 assume ds:nothing
_F000:E2B3 mov eax, [si]
_F000:E2B6 mov dword ptr [si], 0A55A55AAh
_F000:E2BD mov dword ptr [si+4], 5AA5AA55h
_F000:E2C5 wbinvd
_F000:E2C7 mov ax, 4000h
_F000:E2CA mov ds, ax
_F000:E2CC assume ds:nothing
_F000:E2CC mov eax, [si]
_F000:E2CF mov dword ptr [si], 5AA5AA55h
_F000:E2D6 mov dword ptr [si+4], 0A55A55AAh
_F000:E2DE wbinvd
_F000:E2E0 xor ax, ax
_F000:E2E2 mov ds, ax
_F000:E2E4 assume ds:nothing
_F000:E2E4 cmp dword ptr [si], 0A55A55AAh
_F000:E2EB jnz short loc_FE2F7
_F000:E2ED cmp dword ptr [si+4], 5AA5AA55h
_F000:E2F5 jz short loc_FE30E
_F000:E2F7
_F000:E2F7 loc_FE2F7: ; CODE XREF: ram_cache+235j
_F000:E2F7 mov cx, 52h ; 'R'
_F000:E2FA mov sp, 0E300h
_F000:E2FD jmp pci_read_dev
_F000:E2FD ; ---------------------------------------------------------------------------
_F000:E300 dw offset loc_FE302
_F000:E302 ; ---------------------------------------------------------------------------
_F000:E302
_F000:E302 loc_FE302: ; DATA XREF: ram_cache+24Ao
_F000:E302 and al, 3Fh
_F000:E304 or al, 40h ; set 256KB, leave type and mode as is
_F000:E306 mov sp, 0E30Ch
_F000:E309 jmp pci_write_dev
_F000:E309 ; ---------------------------------------------------------------------------
_F000:E30C dw offset loc_FE30E
_F000:E30E ; ---------------------------------------------------------------------------
_F000:E30E
_F000:E30E loc_FE30E: ; CODE XREF: ram_cache:loc_FE267j
_F000:E30E ; ram_cache+23Fj
_F000:E30E ; DATA XREF: ...
_F000:E30E mov cx, 52h ; 'R'
_F000:E311 mov sp, 0E317h
_F000:E314 jmp pci_read_dev
_F000:E314 ; ---------------------------------------------------------------------------
_F000:E317 dw offset loc_FE319
_F000:E319 ; ---------------------------------------------------------------------------
_F000:E319
_F000:E319 loc_FE319: ; DATA XREF: ram_cache+261o
_F000:E319 mov ah, al
_F000:E31B and ah, 0F0h
_F000:E31E cmp ah, 80h ; 'Ç' ; test if 512KB was selected?
_F000:E321 jnz short loc_FE325
_F000:E323 or al, 30h ; if 512KB then set PB
_F000:E325
_F000:E325 loc_FE325: ; CODE XREF: ram_cache+26Bj
_F000:E325 or al, 3 ; set Enabled; miss forced on reads/writes
_F000:E327 mov sp, 0E32Dh
_F000:E32A jmp pci_write_dev
_F000:E32A ; ---------------------------------------------------------------------------
_F000:E32D dw offset cache_prefll2
_F000:E32F ; ---------------------------------------------------------------------------
_F000:E32F
_F000:E32F cache_prefll2: ; DATA XREF: ram_cache+277o
_F000:E32F mov dx, 8000h
_F000:E332
_F000:E332 loc_FE332: ; CODE XREF: ram_cache+28Aj
_F000:E332 mov ds, dx
_F000:E334 assume ds:nothing
_F000:E334 mov cx, 4000h
_F000:E337 xor si, si
_F000:E339 rep lodsd
_F000:E33C sub dx, 1000h
_F000:E340 jnz short loc_FE332
_F000:E342 mov al, 0
_F000:E344 mov sp, 0E34Ah
_F000:E347 jmp CMOS_L1cache
_F000:E347 ; ---------------------------------------------------------------------------
_F000:E34A dw offset loc_FE34C
_F000:E34C ; ---------------------------------------------------------------------------
_F000:E34C
_F000:E34C loc_FE34C: ; DATA XREF: ram_cache+294o
_F000:E34C shr esp, 10h
_F000:E350 clc
_F000:E351 retn
_F000:E351 ram_cache endp
_F000:E351
_F000:E352
_F000:E352 ; =============== S U B R O U T I N E =======================================
_F000:E352
_F000:E352
_F000:E352 cache_test proc near ; CODE XREF: ram_cache+16Fj
_F000:E352 ; ram_cache+186j ...
_F000:E352 cld
_F000:E353 mov ax, 1000h
_F000:E356 mov ds, ax
_F000:E358 assume ds:nothing
_F000:E358 xor si, si
_F000:E35A mov cx, 1000h
_F000:E35D rep lodsd
_F000:E360 mov ax, 1000h
_F000:E363 mov es, ax
_F000:E365 assume es:nothing
_F000:E365 xor di, di
_F000:E367 mov eax, 0A55A55AAh
_F000:E36D mov edx, 3C3C33CCh
_F000:E373 mov cx, 100h
_F000:E376
_F000:E376 loc_FE376: ; CODE XREF: cache_test+38j
_F000:E376 mov es:[di], eax
_F000:E37A add di, 4
_F000:E37D mov es:[di], edx
_F000:E381 add di, 4
_F000:E384 not eax
_F000:E387 not edx
_F000:E38A loop loc_FE376
_F000:E38C wbinvd
_F000:E38E mov cx, 100h
_F000:E391 xor di, di
_F000:E393 mov eax, 0A55A55AAh
_F000:E399 mov edx, 3C3C33CCh
_F000:E39F
_F000:E39F loc_FE39F: ; CODE XREF: cache_test+65j
_F000:E39F cmp es:[di], eax
_F000:E3A3 jnz short loc_FE3BB
_F000:E3A5 add di, 4
_F000:E3A8 cmp es:[di], edx
_F000:E3AC jnz short loc_FE3BB
_F000:E3AE add di, 4
_F000:E3B1 not eax
_F000:E3B4 not edx
_F000:E3B7 loop loc_FE39F
_F000:E3B9 clc
_F000:E3BA retn
_F000:E3BB ; ---------------------------------------------------------------------------
_F000:E3BB
_F000:E3BB loc_FE3BB: ; CODE XREF: cache_test+51j
_F000:E3BB ; cache_test+5Aj
_F000:E3BB stc
_F000:E3BC retn
_F000:E3BC cache_test endp

It does something with PB, but I dont understand the logic yet. Cache detection starts at cache_detect.
TLDR:
512KB Async Normal L2 cache operation (dependent on SGS)
cache_prefill
256KB Async Disabled; tag invalidate on reads
runs memory read test cache_test
If memory test is successful: try 256KB PB Disabled; tag invalidate on read
_If memory test is successful: set 0KB Async Normal L2 cache operation (dependent on SGS) and exit? wtf this looks flipped on its head
if not try 512KB PB Disabled; tag invalidate on reads
_if memory test is successful: run another test just in case
__if successful: set Enabled; miss forced on reads/writes, Exit
__if not set 256KB in previously selected mode (so PB), Exit
_if not set 256KB in previously selected mode (so PB), Exit
...
aaa my head, its too much, gotta make a break 😀 I hope someone else will look at it and decode the logic before I come back 😜

Reply 62 of 110, by feipoa

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Nice decoding work here. It can be painful making sense out of someone else's logic, be it code or personal decisions in life.

Based on the values for bits 0:1, it only makes sense that PB is tested for - it fails the test, thus is disabled and is why we end up with 0010xx11. There's some aspect of hardware on the board that isn't getting along.

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Reply 64 of 110, by feipoa

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OK, I'll test it when you're ready. I'll probably be putting my hardware away in the next few days though.

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Reply 65 of 110, by rasz_pl

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ok with fresh eyes that bios code still looks wrong 😒
TLDR:
cache_test:
ok clc, take next jnb
bad stc, ignore jnb

_F000:E1F7 mov al, 0A2h ; 'ó' ; 512KB Async Normal L2 cache operation (dependent on SGS)
_F000:E201 cache_prefill:
ok, this is just initializing all potential possible cache in Async mode, makes me think PB cache is still capable of working in Async mode

_F000:E218 mov al, 61h ; 'a' ; 256KB Async Disabled; tag invalidate on reads
_F000:E225 jmp cache_test
_F000:E22A jnb short loc_FE26A
lets say you have 256KB of cache working, and PB is capable of working in sync mode, means we are taking this jump

_F000:E26D mov al, 41h ; 'A' ; 256KB PB Disabled; tag invalidate on read
_F000:E27A jmp cache_test
_F000:E27F jnb short loc_FE25A
ok, now it tests if our 256KB of cache that previously worked in Async mode can work in PB mode, it can so we take next jump

_F000:E25D mov al, 22h ; '"' ; 0KB Async Normal L2 cache operation (dependent on SGS)
_F000:E267 jmp loc_FE30E
what the F? so it made sure we got PB cache and .. set it to 0KB effectively disabling it, lets take next jump

_F000:E31E cmp ah, 80h ; 'Ç' ; test if 512KB was selected?
_F000:E321 jnz short loc_FE325
_F000:E323 or al, 30h ; if 512KB then set PB
this piece makes sure that if 512KB is detected then it must be in PB mode so force turning that, we dont have 512 so we jnz skip that

_F000:E325 or al, 3 ; set Enabled; miss forced on reads/writes
_F000:E32A jmp pci_write_dev
and this is enabling cache, we end up with 0010XX11, looks familiar? 😐

cache_prefll2:
seems after final setting of 52h we need to perform reads of all potential cache buckets to sync cache with ram

_F000:E347 jmp CMOS_L1cache
_F000:E34C shr esp, 10h
_F000:E350 clc
_F000:E351 retn
and thats it

Now lets assume we have 256KB of Async onboard:

_F000:E1F7 mov al, 0A2h ; 'ó' ; 512KB Async Normal L2 cache operation (dependent on SGS)
_F000:E201 cache_prefill:
_F000:E218 mov al, 61h ; 'a' ; 256KB Async Disabled; tag invalidate on reads
_F000:E225 jmp cache_test
_F000:E22A jnb short loc_FE26A
_F000:E26D mov al, 41h ; 'A' ; 256KB PB Disabled; tag invalidate on read
_F000:E27A jmp cache_test
_F000:E27F jnb short loc_FE25A
Not PB cache this time, we dont take the jnb

_F000:E284 mov al, 61h ; 'a' ; 256KB Async Disabled; tag invalidate on read
_F000:E291 jmp cache_test
wait, so it sets 256KB Async AGAIN, runs cache_test AGAIN, but doesnt bother checking result this time, jumps straight to

_F000:E31E cmp ah, 80h ; 'Ç' ; test if 512KB was selected?
_F000:E321 jnz short loc_FE325
_F000:E323 or al, 30h ; if 512KB then set PB
this piece makes sure that if 512KB is detected then it must be in PB mode so force turning that, we dont have 512 so we jnz skip that

_F000:E325 or al, 3 ; set Enabled; miss forced on reads/writes
_F000:E32A jmp pci_write_dev
and this is enabling cache, we end up with 0110XX11, working 256KB of async cache.

As far as I can read it this bios is incapable of turning on 256KB of PB cache? Someone smarter than me please sanity check me!

attached bios dgaf, just sets 43 (0100 0011) 256KB PB and jumps to cache_prefll2:. It works in 86BOX forcing 256KB PB no problem 😀
[attachment=-1]Clipboard01.png[/attachment]

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Last edited by rasz_pl on 2022-11-25, 13:01. Edited 1 time in total.

Reply 66 of 110, by feipoa

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That's odd that the code is wanting 512K of pipeline burst SRAM. The board manual states that only Async. DIP SRAM can be 512K, whereas 256K is OK for ASYNC and PBSRAM.

The BIOS for which motherboard did you mod? I'll try it out in a few hours.

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Reply 68 of 110, by feipoa

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Used an external programmer to write an EEPROM, W29EE011-15. The system turned on, but it hangs right before it would normally boot from a floppy or HDD:

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Next, I set L2 to disabled in the BIOS, and it booted fine. I ran CTCHIP34 and it shows the mode is at least set to PB SRAM. Can you also set the size to 256K?

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Reply 69 of 110, by rasz_pl

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feipoa wrote on 2022-11-22, 08:07:

Used an external programmer to write an EEPROM, W29EE011-15. The system turned on, but it hangs right before it would normally boot from a floppy or HDD:

Its before HDD detection, still deep in the bios
3E Try to turn on level 2 cache
BF 1.Program the rest of the chipset's value according to setup (later setup value program)
41 Initialize floppy disk drive controller
42 Initialize hard drive controller

3E is where BIOS changes 2 lowest 52h bits from 11 to 01.
at this point Im starting to think there might be something wrong with the soldering 🙁 It might look fine but needs another go?
Can you try with 50MHz fsb? Or Cache really needs those bypass caps from later revision, you could try bodging a few 100nF (right on top of cache chips) connecting ground and power pins directly

feipoa wrote on 2022-11-22, 08:07:

Next, I set L2 to disabled in the BIOS, and it booted fine. I ran CTCHIP34 and it shows the mode is at least set to PB SRAM. Can you also set the size to 256K?

No, because two upper bits are used for both size and disabling and this point in the code.
You can disable cache setting size to 0, or setting two lower bits to 11 theoretically "Enabled" but "miss forced on reads/writes" aka cache is ignored. You could probably also set 10 (Disabled; tag invalidate on reads aka bios clears TAG) but bios doesnt do that.
Edit: just realized I also got fooled by the order of two lower bits when commenting bios code, but sadly that doesnt change anything 🙁

Im thinking of a way to compile this piece of bios cache test/initialization routine (L1 disable, cache_prefill, cache_test, L1 enable) into standalone dos program to bypass need for relying on bios and bios modding. cache_test is memory destructive (repeatedly fills whole ram with A55A55AAh 3C3C33CCh 5AA5AA55h C3C3CC33h) so needs modification to not overwrite lower 512KB of dos ram. But it would still make CPU start using L2 for the ram this program would be loaded to 🙁 Im assuming in bios case chipset defaults to not caching BIOS rom area. Perhaps instrumenting cache_test to look where it fails with your soldered PB cache would give us some clues, like is it failing totally? or maybe only every 2 bytes? maybe only some bits? or only some specific ram range?

Reply 70 of 110, by majestyk

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Just because I had a missing component there recently and cache was detected as "none" - The pins "CE2" (pin97) of both SRAMS must be connected, they also must be connected to pin 26 of the TAG chip AND HA18 plus this line must be pulled up with a 10K resistor to VcpuIO.

Pins 92 (CE2#) must be connected and pulled down (22R in my case)
(This was on a HX board but probably FX is the same situation)

Reply 72 of 110, by feipoa

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majestyk, I'm not at any datasheets or my computer at the moment, could you clarify which IC HA18 and VcpuIO are on and which pin numbers?

rasz_pl, did you want me to add 100 nF between every Vcc and GND, or just the ones that v1.32 added? If I recall correctly, they added one on only one VCC/GND, and the other two were on two different VCCQ/GNDQ. The existing cap near the PBSRAM currently connect CLK to GND with something in the two-digit pF range, something like 50 pF.

re: soldering, I have already triple checked this with DMM. I also tried to move all the pins by force to ensure it was not the flux holding the pins in place. When that happens, all it takes is a gentle flex of the PCB (or even time) to gap the contact.

It is possible that desoldering the SRAM chips from the COAST module killed one of them, but I'd have to desolder them and put them back onto the COAST to test again. I don't think they died from the heat. I've desodered and resoldered QFP-100 many times without issue, but maybe these were close to failure already?

I can try 50 MHz. Keep in mind that there aren't any SRAM timing options in the BIOS to adjust.

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Reply 73 of 110, by rasz_pl

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feipoa wrote on 2022-11-22, 21:11:

majestyk, I'm not at any datasheets or my computer at the moment, could you clarify which IC HA18 and VcpuIO are on and which pin numbers?

VcpuIO is the ~3 something V supply rail going to SRAMs

feipoa wrote on 2022-11-22, 21:11:

rasz_pl, did you want me to add 100 nF between every Vcc and GND, or just the ones that v1.32 added? If I recall correctly, they added one on only one VCC/GND, and the other two were on two different VCCQ/GNDQ.

good question, look at 32Kx32_pipeline_burst_SRAM_for_Asus.JPG and copy that
pin 4
pin 41
pin 54
pin 77
pin 91
at least 6 bypass caps just for the two big cache chips on your coast module. The way to do it is glue 2-3 100nf capacitors on top of each cache chips and use shortest wires possible to connect VCC and corresponding close by GND to them, so for example one cap Pins 4 - 5, another Pins 70 - 71.

Curiously also pin 31 MODE seems to have 100nF caps on the COAST. It looks like its permanently pulled low or high and those are 3 additional bypass caps. So 9 in total.

feipoa wrote on 2022-11-22, 21:11:

The existing cap near the PBSRAM currently connect CLK to GND with something in the two-digit pF range, something like 50 pF.

so absolutely zero bypass? brilliant design 😀

feipoa wrote on 2022-11-22, 21:11:

re: soldering, I have already triple checked this with DMM. I also tried to move all the pins by force to ensure it was not the flux holding the pins in place. When that happens, all it takes is a gentle flex of the PCB (or even time) to gap the contact.

It is possible that desoldering the SRAM chips from the COAST module killed one of them, but I'd have to desolder them and put them back onto the COAST to test again. I don't think they died from the heat. I've desodered and resoldered QFP-100 many times without issue, but maybe these were close to failure already?

no idea, but we are at a stage where cache is 100% reliably being turned on (modded bios) and it still doesnt work so something else is wrong. Adding decoupling caps is a good start.

Reply 74 of 110, by feipoa

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Looking at the UMC 256K COAST module for which pins have caps:

Left chip:
C3 cap goes to VCCQ on pin 77
C7 cap goes to GM#, or pin 88
C10 cap goes to CE2, or pin 97
C11 cap goes to MODE, or pin 31
C1 and C9 go to 5V plane

Right chip:
C4 cap goes to VCCQ on pin 77
C5 cap goes to VCCQ on pin 54
C8 cap goes to VCC on pin 41
C12 cap goes to MODE, or pin 31
C6 and C14 go to VCC plane
C13 goes to 5V plane

Other caps on the PCB:
C2 goes to TAG 5V

Looking at another UMC COAST module, this one with 512K with four 32kx32k chips, looking at front side:

Left chip:
C4 cap goes to VCC on pin 41
C1, C2, C3 go to VCC plane

Right chip:
C6 cap goes to VCC on pin 91
C5, C7, C8 goes to VCC plane

Looking at ASUS motherboard v1.32,

Left chip:
Cap goes to VCCQ on pin 61
Cap goes to VCC on pin 41

Right chip:
Cap goes to VCCQ on pin 77
Cap goes to VCC on pin 41

There isn't a lot consistency between these, except for pin 41. I think I will start with what Asus v1.32 did, test, then add a few more, test.

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Reply 75 of 110, by majestyk

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The wiring is a bit easier here, than I thought.
HA18 (host address line 18) comes into play only when there´s 512K L2 cache. The pins CS2 and CS2# are needed as soon as you have a two bank situation that is when you have 4 chips (4 onboard or 2 onboard and 2 on a COAST stick. There´s no CELP slot on your board and you didn´t solder 2 x 64Kx32 PB-chips.
In your situation - to be sure there´s nothing missing - you should check these connections:

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At the TAG chip there are 2 unused address lines: 14 and 13. A14 (pin 1) is usually grounded anyway, but check the situation at A13 (pin 26).

Amd then there´s a resistor R62 in the "ADSP" line (pin 84 at the left PB-chip) that comes from the CPU (address status). I wonder if this has to be the same value as in the async. situatiuon?

For comparison, here´s the async. wiring:

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ADSP and some more aren´t needed here and you can see where the 13 buffers / transceivers come (came) into play. I would focus especially on the lines that were not needed for async operation and make sure they really connect to the TSC or CPU now.

Reply 77 of 110, by feipoa

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While you were doing your write-up, I was giving my eyes a painful exercise of DMM trace tracking. I checked all pins on Figure 5 from the 437FX datasheet, except for the 64 data pins from PBSRAM to 438FX TDP chip. Highly unlikely that Asus would goof that up?

I assume the ordering of the address pins doesn't matter? There is symmetry with some pins, but not others.

For example,
CPU LEFT-PBSRAM RIGHT-PBSRAM
A3 - A0 - A0
A4 - A1 - A1
A5 - A10 - A13
A6 - A11 - A14
.
.
.

I tried 50 MHz FSB, but it still wouldn't boot using the rasz_pl modded BIOS.

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Reply 78 of 110, by feipoa

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I used double-sided tape to make the caps easy to remove later and soldered on four 0.1 uF caps where Asus MB v1.32 has their extra caps. I tried booting with the modded BIOS, but the result was the same. It hangs before trying to boot from a floppy or disk.

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Reply 79 of 110, by rasz_pl

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🙁

Bios cache_test procedure:

_F000:E352 cache_test      proc near
_F000:E352 cld
_F000:E353 mov ax, 1000h
_F000:E356 mov ds, ax
_F000:E358 assume ds:nothing
_F000:E358 xor si, si
_F000:E35A mov cx, 1000h
_F000:E35D rep lodsd

Load 16KB from between 64-80KB.
- why?
- why only 16KB?
- why start at 10000h?
I can understand doing this while L2 cache is in "Disabled; tag invalidate on reads" mode to invalidate whole thing. But here its being called with fully enabled cache.

_F000:E360                 mov     ax, 1000h
_F000:E363 mov es, ax
_F000:E365 assume es:nothing
_F000:E365 xor di, di
_F000:E367 mov eax, 0A55A55AAh
_F000:E36D mov edx, 3C3C33CCh
_F000:E373 mov cx, 100h
_F000:E376
_F000:E376 loc_FE376:
_F000:E376 mov es:[di], eax
_F000:E37A add di, 4
_F000:E37D mov es:[di], edx
_F000:E381 add di, 4
_F000:E384 not eax
_F000:E387 not edx
_F000:E38A loop loc_FE376
_F000:E38C wbinvd
_F000:E38E mov cx, 100h
_F000:E391 xor di, di
_F000:E393 mov eax, 0A55A55AAh
_F000:E399 mov edx, 3C3C33CCh
_F000:E39F
_F000:E39F loc_FE39F:
_F000:E39F cmp es:[di], eax
_F000:E3A3 jnz short loc_FE3BB
_F000:E3A5 add di, 4
_F000:E3A8 cmp es:[di], edx
_F000:E3AC jnz short loc_FE3BB
_F000:E3AE add di, 4
_F000:E3B1 not eax
_F000:E3B4 not edx
_F000:E3B7 loop loc_FE39F
_F000:E3B9 clc
_F000:E3BA retn
_F000:E3BB ; ---------------------------------------------------------------------------
_F000:E3BB loc_FE3BB:
_F000:E3BB stc
_F000:E3BC retn

Store 2KB of magic numbers at 64KB, flush cache, check if 2KB of magic numbers is still there.
- why only 2KB?
- why start at 10000h?
- I dont know if Ram is initialized properly at this point, but we seem to be relying on it being there (wbinvd supposed to flush and empty cache)? and there being more than 64KB of it installed safe assumption with 72pin simms I giess 😜)

Looks like L2 cache can only work in Write Back mode on 430FX. This test fully depends on the fact whatever is written to ram goes into cache chips first. We are checking if write back wrote exactly what we intended.

What I can do now is write another small mod that will let you read back what bios stored in this 2KB window at 10000h using POST card display when pressing "~1234567890-=<backspace>Tab" keys. Every key is one value from 0 to 15. I can slightly modify my previous crappy bios mod I wrote here Re: Early P5 + P54C (Socket 4 + Socket 5) mainboard

label:
mov cx, 1000
myloop:
loop myloop

mov DX, 0x80
in al, 0x64
in al, 0x60

cmp al, 0x29
jne dalej
mov al, 1
dalej:
cmp al, 0x10
jnb label

dec al
out DX, AL

mov cx, 1000
myloop2:
loop myloop2

or al,0x80
out 0x70, AL
in AL, 0x71
out DX, AL
jmp label