Have you identified which signals the jumpers switch, since a sip is just a sim with legs and the pinout is available and for the dip ram the pdf with pinout is available.

The chipset datasheet is available on the internet. The combination of the 82C211, 82C212 and 82C215 is collectively called the CS8221 (which is the title of the data sheet). The 82C212 has three pins that exist in a separate copy per bank: /RASx (80, 79, 78 and 77), /CASx0 (41, 39, 37 and 35) and /CASx1 (44, 40, 38 and 36). As you have 12 jumpers and 4 banks of RAM, it is likely that each set of 3 jumpers selects a source "x" for a specific physical bank (DIP bank 0, DIP bank 1, first SIPP bank, second SIPP bank).

The position of the RAS pin on both SIPP and DIP chips is easily found on the internet (SIPP pinout is identical to SIMM pinout). Each SIPP socket only gets one CAS pin (either CASx0 or CASx1), but the two SIPP sockets on a bank are connected to the different CAS lines. For DIP, there is a group of 9 chips per bank that is connected to CASx0 and another group of 9 connected to CASx1. If you buzz out the connections between chipset, jumpers and RAM sockets, a table containing valid RAM configurations and the required jumper settings can easily be derived. If you just buzz out all the RAS connections for all banks, and confirm for some of the other jumpers that they are connected to CAS signals, that should be enough. No need to bother with all the CAS signalling, which will be tedious and yield redundant information.

Just checked the RAS and CAS lines between memory chips / sockets and jumpers:

______________________
x-CAS02-x | x-RAS2-x | x-RAS3-x

x-CAS21-x | x-RAS0-x | x-RAS1-x

x-CAS22-x | x-CAS31-x | x-CAS32-x

x-CAS01-x | x-CAS12-x | x-CAS11-x
_______________________

(first digit=bank, second digit=DIP column / SIPP module number)

I now have to trace the connections from pins 1 and 3 of each jumper to the chipset.
All lines are passing through buffers so it´ll take a while.

mkarcher wrote on 2023-07-23, 08:39:

The chipset datasheet is available on the internet. The combination of the 82C211, 82C212 and 82C215 is collectively called the CS8221 (which is the title of the data sheet). The 82C212 has three pins that exist in a separate copy per bank: /RASx (80, 79, 78 and 77), /CASx0 (41, 39, 37 and 35) and /CASx1 (44, 40, 38 and 36). As you have 12 jumpers and 4 banks of RAM, it is likely that each set of 3 jumpers selects a source "x" for a specific physical bank (DIP bank 0, DIP bank 1, first SIPP bank, second SIPP bank).

The position of the RAS pin on both SIPP and DIP chips is easily found on the internet (SIPP pinout is identical to SIMM pinout). Each SIPP socket only gets one CAS pin (either CASx0 or CASx1), but the two SIPP sockets on a bank are connected to the different CAS lines. For DIP, there is a group of 9 chips per bank that is connected to CASx0 and another group of 9 connected to CASx1. If you buzz out the connections between chipset, jumpers and RAM sockets, a table containing valid RAM configurations and the required jumper settings can easily be derived. If you just buzz out all the RAS connections for all banks, and confirm for some of the other jumpers that they are connected to CAS signals, that should be enough. No need to bother with all the CAS signalling, which will be tedious and yield redundant information.

just looked at the datasheet for the CS8221... 8 CAS lines, 4 RAS lines, max 8Meg of RAM...
but
looking at the photo, where is the 82C212 ? is it replaced by the 82C218 and does it have a datasheet/pinout reference ?
nevermind.. mistook 212B for 218 :-p

I tested the 4 RAS lines today, they are wired as follows:

RAS bank0 (jumper pin1) -> 33R -> buffer O3/I3 -> 82C212 pin80
RAS bank1 (jumper pin1) -> 33R -> buffer O7/I7 -> 82C212 pin79
RAS bank2 (jumper pin1) -> 33R -> buffer O2/I2 -> 82C212 pin78
RAS bank3 (jumper pin1) -> 33R -> buffer O0/I0 -> 82C212 pin77

Every RAM bank (DIP and SIPP) is connected to one of the RAS outputs of the 82C212 when the respective jumpers are set to 1-2.
So I assumed that probably all jumpers need to be set to 1-2 to address all 4 RAM banks.
And indeed in this case all RAM IS detected IF in the BIOS chipset register setup for the 82C212 in registers "6AH" and "6CH" the number of banks is set to "0" -> "one bank in non-interleaved mode".
I´m quite sure I did test with all jumpers set to 1-2, but since there were some BIOS resets during my tests, I cannot rule out the registers were set to "2 banks" at some time.
According to the datashees the chipset supports Interleave when there are 256K chips in the DIP banks and 1MB chips on the SIPP sticks:

But when I enable Interleave for banks 1+2 only or banks 1+2 and 2+3, just 1MB RAM is detected (in banks 0+1), when I enable Interleave for banks 2+3 only all 5MB are detected.
As soon as "Address map for RAM in 512K to 640K area" is set to "1=RAM on system board" and "Relocate DRAM at 640K to above 1MB" is set to "Do not relocate RAM", everything seems to work fine.

majestyk wrote on 2023-07-24, 08:43:

and "Relocate DRAM at 640K to above 1MB" is set to "Do not relocate RAM", everything seems to work fine.

That's hidden in the data sheet. Look at page 50, description of register RB7, bit 6. "A one (default) relocates local RAM from 0A0000-0FFFF to 100000-15FFFF, provided total local RAM is 1Mbyte only". So clearly relocation does not work if more than 1MB is installed, but the datasheet sounds like this setting would be ignored if more than 1MB is installed.

majestyk wrote on 2023-07-24, 08:43:

And indeed in this case all RAM IS detected IF in the BIOS chipset register setup for the 82C212 in registers "6AH" and "6CH" the number of banks is set to "0" -> "one bank in non-interleaved mode".

I believe that it works this way, but it makes no sense. The setting 0 in bit 5 of 6AH and 6CH is meant to tell the chipset that only 512KB of DIP RAM and only 2MB of SIPP RAM is installed. It is quite plausible that the POST probes for the installed memory and auto-configures these bits.

majestyk wrote on 2023-07-24, 08:43:

But when I enable Interleave for banks 1+2 only or banks 1+2 and 2+3, just 1MB RAM is detected (in banks 0+1), when I enable Interleave for banks 2+3 only all 5MB are detected.

Do you get to choose the configuration for bank 0+1? The chipset allows 256K+64K, 256K(+256K) and 1M(+1M). If you choose 256K+64K, interleaving will not work.

Each pair of banks can be configured seperately.
Register "6AH" for banks 0/1 (DIP):

and 6CH for banks 2/3 (SIPP):

The second value right of the entry for chip-size is for enabling interleave for the respective pair of banks. Here it´s "1" for enable.

majestyk wrote on 2023-07-24, 17:37:

Register "6AH" for banks 0/1 (DIP):

and 6CH for banks 2/3 (SIPP):

If 5MB are working at that configuration, that looks like the correct and optimal setting, indeed.