I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits.

mkarcher wrote on 2023-04-04, 16:45:

I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits.

Great, that should speed the thing up if that work!
Thanks

Rav wrote on 2023-04-04, 17:06:

mkarcher wrote on 2023-04-04, 16:45:

I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits.

Great, that should speed the thing up if that work!
Thanks

I found the following settings:

112
2  10: Hidden refresh (Disabled, Enabled)
316
4  03: DRAM read timing (slow, normal, fast, fastest)
5  0c: DRAM write timing (slow, normal, fast, fastest)
617
7  03: Cycle Check point (resvd, Fast, Normal, Slow)
8  30: HITMJ sampling time (2t, 3t, 4t, 5t)
919
10  20: Cache write timing (0WS, 1WS)
11  40: Cache read timing (0WS, 1WS)
121A
13  C0: RAS-to-CAS delay (2t, 4t, 6t, resvd)
141E
15  04: VESA L2 Cache Write (normal, long)
16  08: VESA L2 Cache Read (normal, long)
17  10: VESA master cycle ADSJ (normal, delay)
1820
19  07: AT Bus clock select (7.19MHz, CLK2/4, CLK2/5, CLK2/6, CLK2/8, CLK2/10, CLK2/12, resvd)
20  70: Polling clock select (14.318MHz, CLK2, CLK2/2, CLK2/3, CLK2/4, 28.636, resvd, resvd)
2122
22  01: IO Recovery (Disabled, Enabled)
23  02: Onboard IO Recovery (Disabled, Enabled)
24  04: ISA write cycle (0WS, 1WS)
2525:
26  03: 16 Bit ISA I/O command (0WS, 1WS, 2WS, 3WS)
27  0C: 16 Bit ISA memory command (0WS, 1WS, 2WS, 3WS)
28  30: slow refresh (Disable, 30us, 60us, 120us)
29  C0: 32 Bit ISA wait time (2t, 4t, 6t, 8t)
3027:
31  01: Local ready syn mode (SYN, BYPASS)
32  02: Internal ADS delay (Disabled, Enabled)
33  30: LDEVJ Check Point Delay (disable, 1 CKL2, 2 CLK2, 3 CLK2)
34
35Autoconfig
36FSB = CLK2 (for 486, so actually CLK2 is not CLK2 but CLK)
37FSB       16/0F  17/03  19/60  20/77  27/30
3816-25      05     01     00     00     20
3933         05     01     40     01     30
4040         05     01     60     02     30
4150         05     01     60     03     30
4225 (DX2)   05     01     00     00     20
4333 (DX2)   05     01     40     01     30
4440 (DX2)   05     01     60     02     30
4525 (DX4)   05     01     00     00     20
4633 (DX4)   05     01     40     01     30
47FSB = CLK2/2 (for 386)
48FSB       16/0F  17/03  19/60  20/77  27/30
4916-25      05     01     00     03     20
5033         05     01     40     04     30
5140         05     01     60     05     30
5250         05     01     60     00     30
5325 (DX2)   05     01     00     03     20
5433 (DX2)   05     01     40     04     30
5540 (DX2)   05     01     60     05     30
5625 (DX4)   05     01     00     03     20
5733 (DX4)   05     01     40     04     30

How to read the register map: The heading is the chipset register index. The indented number is the bitmap for the setting, the possible choices are listed comma-separated in parenthesis.

Auto config tables specify register and affected bits in the header, and the value for those bits in the body of the table.

I don't know how to interpret your finding that register 1D has a lot of effect, and not seeing register 1D in the chipset configuration table at all, OTOH you also reported that your BIOS doesn't update that register.

mkarcher wrote on 2023-04-04, 17:55:

I found the following settings: […]
Show full quote

Rav wrote on 2023-04-04, 17:06:

mkarcher wrote on 2023-04-04, 16:45:

I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits.

Great, that should speed the thing up if that work!
Thanks

I found the following settings:

Copy code to clipboard

112
2  10: Hidden refresh (Disabled, Enabled)
316
4  03: DRAM read timing (slow, normal, fast, fastest)
5  0c: DRAM write timing (slow, normal, fast, fastest)
617
7  03: Cycle Check point (resvd, Fast, Normal, Slow)
8  30: HITMJ sampling time (2t, 3t, 4t, 5t)
919
10  20: Cache write timing (0WS, 1WS)
11  40: Cache read timing (0WS, 1WS)
121A
13  C0: RAS-to-CAS delay (2t, 4t, 6t, resvd)
141E
15  04: VESA L2 Cache Write (normal, long)
16  08: VESA L2 Cache Read (normal, long)
17  10: VESA master cycle ADSJ (normal, delay)
1820
19  07: AT Bus clock select (7.19MHz, CLK2/4, CLK2/5, CLK2/6, CLK2/8, CLK2/10, CLK2/12, resvd)
20  70: Polling clock select (14.318MHz, CLK2, CLK2/2, CLK2/3, CLK2/4, 28.636, resvd, resvd)
2122
22  01: IO Recovery (Disabled, Enabled)
23  02: Onboard IO Recovery (Disabled, Enabled)
24  04: ISA write cycle (0WS, 1WS)
2525:
26  03: 16 Bit ISA I/O command (0WS, 1WS, 2WS, 3WS)
27  0C: 16 Bit ISA memory command (0WS, 1WS, 2WS, 3WS)
28  30: slow refresh (Disable, 30us, 60us, 120us)
29  C0: 32 Bit ISA wait time (2t, 4t, 6t, 8t)
3027:
31  01: Local ready syn mode (SYN, BYPASS)
32  02: Internal ADS delay (Disabled, Enabled)
33  30: LDEVJ Check Point Delay (disable, 1 CKL2, 2 CLK2, 3 CLK2)
34
35Autoconfig
36FSB = CLK2 (for 486, so actually CLK2 is not CLK2 but CLK)
37FSB       16/0F  17/03  19/60  20/77  27/30
3816-25      05     01     00     00     20
3933         05     01     40     01     30
4040         05     01     60     02     30
4150         05     01     60     03     30
4225 (DX2)   05     01     00     00     20
4333 (DX2)   05     01     40     01     30
4440 (DX2)   05     01     60     02     30
4525 (DX4)   05     01     00     00     20
4633 (DX4)   05     01     40     01     30
47FSB = CLK2/2 (for 386)
48FSB       16/0F  17/03  19/60  20/77  27/30
4916-25      05     01     00     03     20
5033         05     01     40     04     30
5140         05     01     60     05     30
5250         05     01     60     00     30
5325 (DX2)   05     01     00     03     20
5433 (DX2)   05     01     40     04     30
5540 (DX2)   05     01     60     05     30
5625 (DX4)   05     01     00     03     20
5733 (DX4)   05     01     40     04     30

How to read the register map: The heading is the chipset register index. The indented number is the bitmap for the setting, the possible choices are listed comma-separated in parenthesis.

That's a good start, THANKS !

So no mention of register 1D (The one I used to get performance improvement so far), interesting.
And that answer my question about register 20!

So far I did many tests.

Register 0x1D, At the end I ended up not using it. While it increase the memory performance, mainly with a 33Mhz bus, the other changes like the dram timing from register 16 do not change anything. Like it ignore it...
Getting rid of the 1D register modification allowed a better improvement while patching the other register.

Register 20, bitmask 07 seam to be **upside down** . Higher number seam to give a lower multiplier, not the other way around. (my board set it to 0x24 for 33, and 0x22 for 40 and 50)
I'm going to post screenphotos of (before) and (after) for comparison of what I was able to achieve so far.

Here 33Mhz.
As we see, the ram read/write is now as fast as the L2 cache read. While move still very low

Stock

After registers patch

Here 40Mhz, There are improvement but there is still something to fix somewhere (the memory subsystem seam to be just plain slower).
At least now the memory stuff are "about equal" as "stock 33".

Stock

Patched

Here 50:
The memory stuff seam to be a little faster than optimized 33 (I suspect that the divider that apply a big malus on the performance is the same on 40 and 50 mhz bus so what I lost between 33 and 40, I got it back between 40 and 50. Minus the L2, don't work at 50fsb.

Stock

Patched

Still have to find what give between 33 and 40Mhz fsb

I look like that all Acer motherboards I did see (based on M1429), have the same exact issue.

mkarcher wrote on 2023-04-04, 17:55:

I found the following settings: […]
Show full quote

Rav wrote on 2023-04-04, 17:06:

mkarcher wrote on 2023-04-04, 16:45:

I downloaded the Award BIOS 2.0 for the A-Trend 1762 from The Retro Web, I will try to dump the setup table from it, which should directly yield a mapping of CMOS options to chipset bits.

Great, that should speed the thing up if that work!
Thanks

I found the following settings:

Copy code to clipboard

112
2  10: Hidden refresh (Disabled, Enabled)
316
4  03: DRAM read timing (slow, normal, fast, fastest)
5  0c: DRAM write timing (slow, normal, fast, fastest)
617
7  03: Cycle Check point (resvd, Fast, Normal, Slow)
8  30: HITMJ sampling time (2t, 3t, 4t, 5t)
919
10  20: Cache write timing (0WS, 1WS)
11  40: Cache read timing (0WS, 1WS)
121A
13  C0: RAS-to-CAS delay (2t, 4t, 6t, resvd)
141E
15  04: VESA L2 Cache Write (normal, long)
16  08: VESA L2 Cache Read (normal, long)
17  10: VESA master cycle ADSJ (normal, delay)
1820
19  07: AT Bus clock select (7.19MHz, CLK2/4, CLK2/5, CLK2/6, CLK2/8, CLK2/10, CLK2/12, resvd)
20  70: Polling clock select (14.318MHz, CLK2, CLK2/2, CLK2/3, CLK2/4, 28.636, resvd, resvd)
2122
22  01: IO Recovery (Disabled, Enabled)
23  02: Onboard IO Recovery (Disabled, Enabled)
24  04: ISA write cycle (0WS, 1WS)
2525:
26  03: 16 Bit ISA I/O command (0WS, 1WS, 2WS, 3WS)
27  0C: 16 Bit ISA memory command (0WS, 1WS, 2WS, 3WS)
28  30: slow refresh (Disable, 30us, 60us, 120us)
29  C0: 32 Bit ISA wait time (2t, 4t, 6t, 8t)
3027:
31  01: Local ready syn mode (SYN, BYPASS)
32  02: Internal ADS delay (Disabled, Enabled)
33  30: LDEVJ Check Point Delay (disable, 1 CKL2, 2 CLK2, 3 CLK2)
34
35Autoconfig
36FSB = CLK2 (for 486, so actually CLK2 is not CLK2 but CLK)
37FSB       16/0F  17/03  19/60  20/77  27/30
3816-25      05     01     00     00     20
3933         05     01     40     01     30
4040         05     01     60     02     30
4150         05     01     60     03     30
4225 (DX2)   05     01     00     00     20
4333 (DX2)   05     01     40     01     30
4440 (DX2)   05     01     60     02     30
4525 (DX4)   05     01     00     00     20
4633 (DX4)   05     01     40     01     30
47FSB = CLK2/2 (for 386)
48FSB       16/0F  17/03  19/60  20/77  27/30
4916-25      05     01     00     03     20
5033         05     01     40     04     30
5140         05     01     60     05     30
5250         05     01     60     00     30
5325 (DX2)   05     01     00     03     20
5433 (DX2)   05     01     40     04     30
5540 (DX2)   05     01     60     05     30
5625 (DX4)   05     01     00     03     20
5733 (DX4)   05     01     40     04     30

How to read the register map: The heading is the chipset register index. The indented number is the bitmap for the setting, the possible choices are listed comma-separated in parenthesis.

Auto config tables specify register and affected bits in the header, and the value for those bits in the body of the table.

I don't know how to interpret your finding that register 1D has a lot of effect, and not seeing register 1D in the chipset configuration table at all, OTOH you also reported that your BIOS doesn't update that register.

Could you point me to the proper tool to extract that?
I am looking for the cache configuration for WT/WB

I did download the same BIOS (atc 1762) and where only able to open it with modbin. There I can clearly see that in the setup it does have WT/WB configurations for internal and external caches. But I don't see any way to extract the setup table from there. I also tried with a few CBROM version without any success.

I also tried with some other ALI1429G board with AMI Bioses, with many amibcp version, all I get is "header not found"

Rav wrote on 2023-09-20, 17:46:

Could you point me to the proper tool to extract that? I am looking for the cache configuration for WT/WB […]
Show full quote

Could you point me to the proper tool to extract that?
I am looking for the cache configuration for WT/WB

I did download the same BIOS (atc 1762) and where only able to open it with modbin. There I can clearly see that in the setup it does have WT/WB configurations for internal and external caches. But I don't see any way to extract the setup table from there. I also tried with a few CBROM version without any success.

I also tried with some other ALI1429G board with AMI Bioses, with many amibcp version, all I get is "header not found"

I loaded the BIOS into a disassembler (IDA in this case), and used my knowledge about Award data structures to manually derive the table. I didn't use any kind of automated tool for that.

mkarcher wrote on 2023-09-20, 21:32:

Rav wrote on 2023-09-20, 17:46:

Could you point me to the proper tool to extract that? I am looking for the cache configuration for WT/WB […]
Show full quote

Could you point me to the proper tool to extract that?
I am looking for the cache configuration for WT/WB

I did download the same BIOS (atc 1762) and where only able to open it with modbin. There I can clearly see that in the setup it does have WT/WB configurations for internal and external caches. But I don't see any way to extract the setup table from there. I also tried with a few CBROM version without any success.

I also tried with some other ALI1429G board with AMI Bioses, with many amibcp version, all I get is "header not found"

I loaded the BIOS into a disassembler (IDA in this case), and used my knowledge about Award data structures to manually derive the table. I didn't use any kind of automated tool for that.

Does Award have a predictable format with regard to mapping CMOS registers to chipset registers? I have looked at much more AMI HiFlex than Award, and as far as I can tell, there is no pattern. There are stubs of code that will read from selected CMOS registers and program the chipset, and most of the time it looks like they picked a CMOS register number somewhat close to the chipset register number, but that's not always possible and they will sometimes reuse some of the bits for some other meaning.

I managed to read the table.
Now I understand why it was missing these 3 options in mkarcher dump:
Internal cache WB/WT
External cache WB/WT
Shadow Bios Cacheable

The only 3 missing for that specific table.
They point to register FF... or FFFF? actually because it have an extra byte stuffed between the "register" and "bit" then one bit 01, then 04 and 08.
Register FF, I don't know if it's the real deal or it's "FF" because there fake menu, But FFh do read 00000101. I assume bit 04 is 0 because my board is configured for 486 (not WB 486).. I could set it back to Cyrix 5x86 tomorrow and see if it's switched to a 1.... But ctcm detect WB so at that point i'm not sure what to think..

I can't modify these, they are read only.

Edit : 08, 04, 01 would make it 0000xy0z, not 00000xyz.

I did poke in the register 19 (the same that have the cache timings) as it would be logical that the WT/WB setting would be there

Here is what I found so far

119:
2  01 - System crash with some garbage on the screen
3  02 - System crash when I exit ctchip
4  04 - Do nothing apparent, no crash, no difference in cache behavior
5  08 - System crash instantly
6  10 - Do nothing apparent, no crash, no difference in cache behavior
7  20 - Write cache timing 0ws/1ws
8  40 - Read cache timing 0ws/1ws
9  80 - System crash instantly

I assume some of these could be cache on/off and maybe there is the WT/WB config too.
But maybe it's just not possible to switch from WB to WT once the system is booted. I assume that if it's set to WB and you switch it to WT or turn the cache off, the chipset might be too stupid to check the dirtiness in the tag and so you end up with uncommitted write and crashs.

Maybe I could try to do ton of memory allocation / writing / reading... before updating the register... So I could trash the cache with useless data before so there is less chance that something important get forgotten there.