Uncommon cache chips, indeed.
5C6404-15 16Kx4
15 ns because of 40 MHz

It looks like it is layouted for one cache bank with 8 chips.

For me it looks like you need 10 64kx4 chips.

x4 cache chips were quite common in the early 90s. On early 486 boards, it's not unusual to find the TAG RAM as 3 x4 chips, to provide 12 tag bits that yield a conveniently big cacheable area even at a mere 32KB of cache. On other boards, the Alter/Dirty bit was stored as a single bit in one of the x4 chips. If you already have x4 chips in your board, it can make sense to just build the data cache from the same cache chips as the tag.

There are no x8 chips in DIP22 or DIP24. The standard case for 8K x 8 chips is DIP28. So the Micro House documentation clearly does not apply to your board. Note that the Micro House documentation shows DIP-28 sockets. This either means they carelessly paced DIP28 pictures on the board graphics ("because cache chips are always DIP28"), or there might be a later revision of your board that indeed has two banks of x8 chips instead of one bank of x4 chips.

I agree that your assignment blue=data, green=tag, cyan=dirty makes a lot of sense - on the other hand, it doesn't make sense that the dirty tag chip can not be upgraded to 64k. Thus I propose a slightly different idea that actually makes sense and works for upgraded cache, too. When you upgrade from 64KB of cache to 256KB of cache, you need two less tag bits for the same cacheable area (assuming the common direct-mapped cache scheme). Possibly, the dirty tag bit (if it is present at all) and 7 address tag bits are located in the "green" chips, and the cyan chip contains two extra address tag bits that are only used in the 64KB cache configuration. In that case, this chip is unused with 256KB cache and thus it does not need to be upgraded to 64K x 4.

Thanks for the good insight here!

Ok, I'm going to acquire some 64k x 4 15ns chips and replace all but the dirty bit chip and see if that will work. It's going to take me a few weeks at least to acquire the chips, but I'll update this thread with my results when I acquire and test them.

Thanks for the help!

Following up on this topic!

Obtained some 64k x 4 (MT5C2564-15) chips and did some testing!

Replaced all the 10 ram chips that were in the dual DIP-22/24 sockets with the new 64k x 4 dip-24 chips, and left the remaining 16K x 4 chip that was in the dip-22 socket. Updated the jumpers and powered the board up. It didn't post.
So I pulled the remaining 16K x 4 chip so the board now had just the 10 new 64k x 4 and tried powering it up again. It worked! Verified with cachecheck and the full 256k was detected. The system was also stable after being powered on for many hours.

Here is an updated pic of the new chip arrangement: https://imgur.com/8y6qB2a

I'm going to update the documentation on theretroweb.com for this board. So that leads me to this question. What is the 11th chip's purpose? It's required for 64k but not 256k. I'd like to document the chip but am unsure if it's a "dirty bit" chip, or a third "tag" chip or what?

Thanks again for all the help!

atari52oo wrote on 2024-01-18, 19:49:

What is the 11th chip's purpose? It's required for 64k but not 256k. I'd like to document the chip but am unsure if it's a "dirty bit" chip, or a third "tag" chip or what?

It seems to confirm this suspicion:

mkarcher wrote on 2023-12-19, 13:33:

the cyan chip contains two extra address tag bits that are only used in the 64KB cache configuration. In that case, this chip is unused with 256KB cache and thus it does not need to be upgraded to 64K x 4.

It's an extra tag chip that is only used if you have a low amount of cache. The design of standard 386/486 L2 implementations works in a way that the cacheable area is 256 times the size of the cache. If one tag bit is deducted for use as "dirty" bit, the cacheable area drops to 128 times the size of the cache. So this means the cacheable area with 8 tag bits (two 64k x 4 chips) and 64KB of cache is limited to 8MB (if there is a dirty bit) or 16MB (if the cache operates in write-through or write-back/always dirty mode). This 11th chip increases the cacheable area in that case, likely by a factor of 4, to make it equal to the cacheable area you can obtain with the 256KB cache you currently installed.

Thank you so much @mkarcher for the information and insight! Time to go update some documentation!