watson wrote on 2024-04-22, 19:09:
Do you perhaps have a VLB fix for the original BIOS? I've been looking for it forever.
I just re-checked my around 7 years old notes about my 4SA (which should be identical to the 4SAW in that regard). The notes say that "the BIOS wrongfully configures the chipset to support a further PCI master instead of VLB support". I tested at that time that fixing the chipset configuration indeed made the VL slot work.
Looking at the 496 datasheet, this clearly indicates that PCI config space register 57h of the chipset, bit 3 is inadvertantly set, while it should be clear instead. Furthermore, at least my copy of the 4SA wires further pins in the way that register 57h bits 2 and 0 should be set to 1, with bit 1 being irrelevant. The correct configuration for the SiS496 on that Soyo board is
- Pin 126: PREQ3# (need to clear 57[0])
- Pin 127: PGNT3# (need to clear 57[0])
- Pin 157: MA11 (need to set 57[2]). This enables support for 64MB and 128MB SIMMs.
- Pin 204: LBD# (need to clear 57[3]). This line is also known as LDEV#, and UMC likes to call it ELBA#.
- Pin 207: LRDY# (need to clear 57[3])
The features you are missing in that configuration:
- Support for a dedicated "dirty bit" chip, allowing twice the cacheable area in WB mode, be allowing 8 tag bits + 1 dirty bit instead of 7/1.
- Support for a double-sided memory module in the fourth memory slot.
- Support for a fourth PCI master using pins 204/207 as REQ/GNT.
These chipset features would require a physically different board, and enabling these features would impair other features, so there is no point in trying to make different BIOSes for different feature sets unless you also do physical modifications to the board.
Hopefully you can edit the initialization for register 57 directly using modbin. If not, I would need to dig up my old disassemblies of the WA911 BIOS to find the position in which that register is misconfigured.
