luckybob wrote:To be quite frank, its not possible. You have a single bank of 512kb chips. Which gives you 256kb. The only upgrade are 1mb chips. thus giving you 512k. HOWEVER, past 256k you will need to upgrade the tag ram. But if you look, your tag ram is the small 256kb chip. That chip cannot be upgraded as the next size up is too big for the hole!
The Shuttle HOT-433 motherboard states that a TAG of 32K x 8 (256 Kbit) is sufficient to instruct a single bank (4 chips) of 128 K x 8 (512 Kbytes of L2 cache). It also mentions that a larger TAG RAM isn't needed until one goes up to 1024 Kbytes of double-banked L2 cache, in which case a 64 K x 8 (512 Kbit) TAG would be required.
Anonymous Coward wrote:It will be of benefit if you run the bus faster than 40MHz....
I am curious how this is determined. I figure 15 ns is 66.67 MHz if you take the inverse. I wonder if it is only sufficient for the cache to be just barely faster than the FSB, or is there some sort of Nyquist criterion here where the cache need be 2.5 times faster than the FSB? And if not, are cache wait states required? I figure that since 15 ns SRAM was used in Socket 5 boards for 66 MHz FSB systems, it must be sufficient for any 486. Oddly enough, the slowest L2 cache setting of 3-2-2 is required for operation at 66 MHz using w/15 ns cache and a 12 ns TAG.
nemesis wrote:...as 32 pin 128k x 8 12ns cache chips
Where did you find a 128K x 8 chip (marked as 1024K) in DIP format which runs at 12 ns? I've only had success finding 32K x 8 chips at 12 ns, which were often found in socket 7 motherboards. If you are going to have 1024 Kbytes of L2 cache, it seems that only a 64K x 8 TAG is required (externally marked as 512K).
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