I played around some more. Changed cache chips, used two 8Kx8 tags... any combination and the 2-1-1-1 still isn't stable in Quake. But if I changed graphic card to an ISA one, then it would work. I guess it has something to do with VLB then. Changed graphics card to CL-5426 VLB but nothing improved. So the final conclusion is that this system stays on 128KB cache 🙁

128KB is a good amount of cache for a DLC. Most boards weren't lucky enough to have any cache at all...

You've probably mistaken DLC for SLC. They both have 1kb of internal cache. But DLC is replacement for 386DX processors, so they usually have external cache from 64KB to 256KB on motherboard. While SLC is replacement for 386SX witch usually don't have any external cache.

256KB gives a nice boost over 128KB if they are on the same latences.

Cant see that boost here

It's strange that 256kb isn't stable with 2-1-1-1. Bank interleaving is supposed to allow for tighter timings. I have a board based on the OPTi 495SX which is a bug fixed version of your chipset, and I have not noticed any problems running 2-1-1-1 with 256kb cache.

I guess its a bug 😉

With 2-1-1-1 Quake crashes within seconds and Win95 reports every imaginable error - from corrupt registry forward... while 3-1-1-1 is rock stable but slower then 2-1-1-1 with 128KB cache.

Or you got one or more bum chips that can't run at tight timings

Just stumbled on my old thread... here is a little update that happened in ~2019. By some coincidence I came across faster chips (12ns) With these it works fine at 2-1-1-1 timings.

I guess one (or more) of your 15nS cache chips was (were) faulty or out of spec. You definitely don´t need 12nS for 40 MHz.

No, it's the mobo. I too have one with OPTi 82C495SLC and with 15ns chips best I can do is 128k with 2-x. The best performance:

386DX 40MHz: 128KiB cache 2-x-x-x, 0 WS
486DX2 (or SX2) 66MHz: 256KiB cache 3-1-1-1, 1 WS

386 can't do bursts so it needs as low primary latency as possible, so 2-x is preferable, even with just 128k, over 3-x with 256k. For proper 486 chips (not DLCs that use 386 bus protocol and timings) cache load bursts are critical for code execution, so 3-x is acceptable so long x = 1. In other words, 3-1-1-1 is better than 2-2-2-2, and you can go for 256k because at this point it will be an improvement over 128k, even if rather small.

WS are for cache write, needed for stability with 256k.

majestyk wrote on 2023-03-13, 14:09:

I guess one (or more) of your 15nS cache chips was (were) faulty or out of spec. You definitely don´t need 12nS for 40 MHz.

I agree the 15ns should do the work (even 20 or 25ns).

I can't say 100% if some chip was specs-faulty. But I tried different sets - known working in other boards.

I have 2-3 of these boards and they all act the same. Only 12ns made the difference.