well, just so you know xeons are exactly 2x as tall as the lowly P2. but there are only 2 iirc, 400 & 450, but3 different cache sizes, 512k, 1mb and 2mb. (6 total if you want to be a completionist)

As for the celerons, theres the 266 & 300 covington, mendocino is kinda outside of your area and would be a gen2 p2

gen2 p2's are the 350,400 &450
and gen 2 celeron (mendocino) were the 266 through 433. (in slot 1) The 300a almost deserves its own special case tbh.

I rigged something together quick.
A suggestion would be to have 3 columns, arranged like this:
Column 1:
Klamath 233
Klamath 266
Klamath 300
Deschutes 266
Deschutes 300
Deschutes 333
Deschutes 350

Column 2:
Deschutes 400
Deschutes 450
Katmai 450
Katmai 500
Katmai 550
Katmai 600

Column 3:
Covington 266
Covington 300
Mendocino 300
Mendocino 333
Mendocino 366
Mendocino 400
Mendocino 433

I'm suggesting this as this particular arrangement would be more visually pleasing to me (even though I would've probably placed the SEPP CPUs in the middle column, but then the numbers don't match up as good but you get the idea 😜). The CPU frequencies are not very important when displayed by this as it will be hard to see at first glance 😀

I'll add a makeshift quick cobbled together paint 😜

Thanks.

I like the idea of putting a separate SECC2 column to the center. More so than filling the space with Xeons.

It is a pity there is no space for SECC 400 & 450 though 🙁

Will need to source the SECC2 variants of 400 Mhz & 450 MHz PIIs which I currently don't have in my collection. Also not sure if my 600 PIII is Katmai or Coppermine, need to check that out.

mpe wrote:

It is a pity there is no space for SECC 400 & 450 though 🙁

So, are you aware that in SECC2, you'll also have variants on the CPU die itself? 350 and 400 are made both in PLGA (metal cover) and OLGA ("open" die). 450 is only made in OLGA AFAIK.

http://www.cpu-world.com/forum/viewtopic.php?t=32582 here's a little more to read about that.

But of course, if you want the backside to be visible rather than the front side, it won't matter though.

I like your layout and consider doing something similar, but with the front of the CPUs exposed 😀

luckybob wrote:

and gen 2 celeron (mendocino) were the 266 through 433. (in slot 1) The 300a almost deserves its own special case tbh.

Was Mendocino actually made in 266?

Oh, and by the way - Covington Celerons also exist in 2 variants - the size of the die cap is 2 different sizes 🤣

H3nrik V! wrote:

Oh, and by the way - Covington Celerons also exist in 2 variants - the size of the die cap is 2 different sizes 🤣

They do? I had never noticed, but I never came across a lot of Covingtons anyway.

mpe wrote:

Thanks. […]
Show full quote

Thanks.

I like the idea of putting a separate SECC2 column to the center. More so than filling the space with Xeons.

It is a pity there is no space for SECC 400 & 450 though 🙁

Will need to source the SECC2 variants of 400 Mhz & 450 MHz PIIs which I currently don't have in my collection. Also not sure if my 600 PIII is Katmai or Coppermine, need to check that out.

If you were to want to add all slot 1 CPUs, you're going to need a bigger display 🤣
Slot 1 also had a lot of Coppermines all the way to 1GHz 😜

H3nrik V! wrote:

luckybob wrote:

and gen 2 celeron (mendocino) were the 266 through 433. (in slot 1) The 300a almost deserves its own special case tbh.

Was Mendocino actually made in 266?

Not afaicr

Tetrium wrote:

H3nrik V! wrote:

Oh, and by the way - Covington Celerons also exist in 2 variants - the size of the die cap is 2 different sizes 🤣

They do? I had never noticed, but I never came across a lot of Covingtons anyway.

Yes they do - was also new to me until recently 🤣 Take a look here: http://www.cpu-world.com/forum/viewtopic.php? … light=covington (you need to be logged in to see the images)

Tetrium wrote:

mpe wrote:

Thanks. […]
Show full quote

Thanks.

I like the idea of putting a separate SECC2 column to the center. More so than filling the space with Xeons.

It is a pity there is no space for SECC 400 & 450 though 🙁

Will need to source the SECC2 variants of 400 Mhz & 450 MHz PIIs which I currently don't have in my collection. Also not sure if my 600 PIII is Katmai or Coppermine, need to check that out.

If you were to want to add all slot 1 CPUs, you're going to need a bigger display 🤣
Slot 1 also had a lot of Coppermines all the way to 1GHz 😜

Yeah, I know. Personally, I'm playing with the idea of making a display of all the differences in appearance of the CPUs, though ..

H3nrik V! wrote:

So, are you aware that in SECC2, you'll also have variants on the CPU die itself? 350 and 400 are made both in PLGA (metal cover) and OLGA ("open" die). 450 is only made in OLGA AFAIK.

Oops. I didn't know about PLGA/OLGA thing. Now I know and it is going to be a problem 😀 My composition won't feel complete any more. Perhaps I should ditch Katmai and focus on making PII a(SECC, SECC2) + Celerons as complete as it could be?

There could be also another thing. I suspect that some PII have 72bit ECC cache interface and some don't. Also some variants have a better TAG SRAM chip with increased cacheable limit. Why is Intel making things so complicated for us collectors?

I already knew about Covington. My 300 has much bigger cap than my 266. I suspected the 300 MHz might be a Mendocino 300A, but tests confirmed it really lacks L2. That means 4 Covington variants. I wonder if they are really binned Mendocino's with disabled L2. Aka Celeron SX.

mpe wrote:

Oops. I didn't know about PLGA/OLGA thing. Now I know and it is going to be a problem :) My composition won't feel complete any […]
Show full quote

H3nrik V! wrote:

So, are you aware that in SECC2, you'll also have variants on the CPU die itself? 350 and 400 are made both in PLGA (metal cover) and OLGA ("open" die). 450 is only made in OLGA AFAIK.

Oops. I didn't know about PLGA/OLGA thing. Now I know and it is going to be a problem 😀 My composition won't feel complete any more. Perhaps I should ditch Katmai and focus on making PII a(SECC, SECC2) + Celerons as complete as it could be?

There could be also another thing. I suspect that some PII have 72bit ECC cache interface and some don't. Also some variants have a better TAG SRAM chip with increased cacheable limit. Why is Intel making things so complicated for us collectors?

I already knew about Covington. My 300 has much bigger cap than my 266. I suspected the 300 MHz might be a Mendocino 300A, but tests confirmed it really lacks L2. That means 4 Covington variants. I wonder if they are really binned Mendocino's with disabled L2. Aka Celeron SX.

One theory about the different die cap is that after the Mendocino came, they used the same lid for the Covingtons, for more lean production. According to the linked thread, it seems to be a date thing - with chips having same sspec actually having different die cap .. Based on that I don't thing they are Mendocinos with disabled cache, but I'm not willing to risk decapping any of my chips to confirm 🤣

Again, from CPU-world a subject I posted about the TAGRAM and cacheable limits. Unfortunately no answers as of yet. http://www.cpu-world.com/forum/viewtopic.php?t=32703

By the way: How did you mount the processors in the frame?

I used a thick double sided sticky tape.

This one:

https://www.amazon.co.uk/Double-Waterproof-Mo … _=fsclp_pl_dp_4

mpe wrote:

I used a thick double sided sticky tape.

This one:

https://www.amazon.co.uk/Double-Waterproof-Mo … _=fsclp_pl_dp_4

Nice! Will it hold the SECC2's also?