Don't have any experience with that particular board.

But most 486 motherboard I've seen had 256kB cache realised as 2 banks of 4x32Kx8 chips in DIP28 sockets + one or two tag/dirty chips. Either one or both of these banks often use 28pin chips in DIP32 socket to allow for upgrade to 512kB (where you use just one bank of 128kx8 chips) or even 1024kB (two banks of f128kx8 chips)

The problem is that the pinout of DIP28 chips is slightly different to those that go to DIP32. They have 2 more address bits, but more importantly the power input moves from pin 28 to pin 32. There is also extra inverted chip enable pin. Moving of jumpers to configure for 128kx8 actually means swapping these pins. Otherwise chips are not powered or have power at CE2 input.

Therefore AFAIK you need to do both software and hardware mod IMHO. Often only the hardware as the board is usually able to find out the cache configuration without changing anything in BIOS. Installing bigger chips and configuring chipset registers isn't enough.

I'd use multimeter to find out the correct jumper positions.

@mpe, as already said, the board works with 4xDIP32 chips. It just never uses more than 256kB.

AFAIK, i need to modify register 51 to start using additional address pin. How should i do it with multimeter?

With the multimeter you can check that:

a) That chips are powered. Should be if they at least somehow works. Do you actually know if the cache actually works (not just being reported during POST)
b) That the extra address bits above A14 are connected between all sockets and to the chipset and so the CE2 input.

You should be able to find out what the jumpers do (where they are connected to).

If the above is confirmed you should also check the tag chip as you need bigger tag/dirty chip for 512k and 1024k compared to 256k.

@mpe,
a) chips are powered and speedsys confirms 256kB of working cache by having a dip of memory speed after 256kB
b) A14 and A15 are all connected between each socket. A16 is not. (This is for 2048 bit chips, right?) On chipset, it's connected to pin 147, 142, 118, 96, 60, 10, 25, 166, 202. (Measured on the U16 socket)

I believe i don't even have a jumper for the first of three bits in register 51, setting the cache size.

Tag chip is fine. 256k is okay for 512kB of cache by datasheet. 256kB would only need 16kB tag, 512kB requires 32kB tag, therefore all is good on tag chip.