I found all of the Cache Flush, Pipelining support (NA pin), and ADS/LOCK pins to be completely motherboard independant.
This is written for both PCB designer & end user. PCB solution underneath.
1) TI486SXL(C)2 Clock Doubling is enabled by software. "Cyrix.exe -cd"
2) TI486SXL(C) L1 Cache is enabled & flushed in the following ways:
-a) Cache Enable.
--i) If BIOS supports "Enable Cache", use this option.
--ii) If BIOS does not support "Enable Cache", Cache must be enabled by software. "Cyrix.exe -e"
-b) Cache flush.
--i) If the FLUSH# pin is supported by the chipset, FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
--ii) If the FLUSH# pin is not supported by the chipset:
---1) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is supported, enable BARB by software. "Cyrix.exe -b"
---2) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is NOT supported, solder a connection from MEMW# on the ISA bus/Cache-Memory Controller to the CPUs MEMW# pin (144/168-pin). FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
---3) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is NOT supported, alternatively solder a connection from MEMW# on the ISA bus/Cache-Memory Controller to the CPUs FLUSH# pin (100/132/144/168-pin). Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
---4) If HOLD# is NOT always sent to the CPU during DMA/master cycles, and the system supports VLB (VESA Local Bus), enable BARB by software. "Cyrix.exe -b"
---5) If HOLD# is NOT always sent to the CPU during DMA/master cycles, and the system does NOT support VLB (VESA Local Bus), solder a NAND gate (two input-high, one output-low) where the two inputs are; an inverted MEMW# pin from the ISA bus/Cache-Memory Controller and the HLDA# pin from the Cache-Memory Controller, and the output is the CPUs FLUSH# pin. Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
--iii) If MEMW# is NOT supported by the chipset, and it is unknown whether HOLD# is always sent during DMA/master cycles:
---1) Solder an OR gate (two input-low, one output-low) where the two inputs are; an inverted M/IO# pin and the W/R# or SO# pin, and the output is the CPUs FLUSH# pin. Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
3) TI486SXL Pipeline support:
-a) If Pipelining is supported, and the NA# pin (active low) is driven, the CPUs NA# pin should be connected & driven by the chipset.
-b) If Pipelining is supported, and the NA# pin (active low) is NOT driven, the CPUs NA# pin should not be connected and should be pulled low with a 100-ohm resistor 0.5W.
-c) If Pipelining is not supported, the CPUs NA# pin should not be connected and should be pulled high with a 10k/20k resistor.
-d) If Pipelining is unknown, the CPUs NA# pin may be connected and pulled high with a 20k resistor.
PCB SOLUTION:
CPU pin MEMW# - give a solder pad to the user
CPU pin FLUSH# - give a solder pad to the user
CPU pin FLUSH# - connect to output of 74LVC1G58 (multi combo function gate). Connect inputs to two set options. Use one only:
-Chipset MEMW# (active low), HLDA# (active high) - give solder pads to user
-Chipset SO# (active low), M/IO# (active high) - give solder pads to user
CPU pin NA# - give jumper selection to user
-no jumper - not connected, 10-20k pullup
-1-2 jumper - connected to 132pin socket, 10-20k pullup (default)
-2-3 jumper - not connected, 100-ohm (0.5w) pulldown
So the user needs look through their manual to see which features their motherboard supports to then select what to do with MEMW/FLUSH, and NA selection. MEMW# & FLUSH# have internal pullups. NA# does not. NA#, ADS# and LOCK# require pullups if the chipset doesn't have them, or a ~20k default pullup for all.
To my understanding, only 386 motherboards with an actual 486 socket support the FLUSH# pin directly. For all other boards you need to see what to do.
All of the information above is untested. From: https://usermanual.wiki/Document/1994TI486SXL … 1822911953/view
If right, the easiest boards (after 486 socketted boards) are boards with Hidden Refresh or VLB support, but you still need to make a choice for the NA# pin.