Which BIOS does the board use? If it has AMIBIOS, you might be able to run AMISETUP V2.99 to unhide options. But, if the BIOS is too old it may not work.
CTCHIP34 is able to modify chipset registers, but it's mostly for 486 and Pentium chipsets. You may have to use DEBUG to do it manually.

so the 16mhz quartz would be for coprocessor?

http://bitsavers.org/components/vti/pc/VTI_VL … nual_199201.pdf
low end 286 chipset retooled for 386sx usage?

BUSOSC 121
Bus Oscillator - Supplied from an external oscillator, this signal is used for
AT Bus operations and for non-TURBO processor cycles. If SYSCLK is to
be derived from TCLK2, the BUSOSC input is used to determine the clock
divisor to be used. During normal operation, the BUSOSC pin can be used
in conjunction with an internal register to select SYSCLK to be TCLK2/2,
TCLK2/4, TCLK2/6, or TCLK2/8. If an oscillator is connected to this pin,
SYSCLK can be programmed to be BUSOSC/2, BUSOSC/4, BUSOSC/6,
or BUSOSC/8.

SYSCLK 152
System Clock - This output is 112, 114, 1 /6, or 118 the frequency of TCLK2
or BUSOSC depending on the BUSOSC pin status and the four lower bits
in the CLKCTL Register. The bus control signals BALE, -IOR, -IOW,
-MEMR and -MEMW are synchronized to SYSCLK

page 44 Programmable AT Bus Clock

I think the 16 MHz quartz is an optional item for asynchronous operation between CPU/Mainboard and the ISA bus.

So the ISA bus can run fixed at 8.33 MHz (16 MHz halved by 2),
no matter what the 4 pin crystal oscillator is running at (or which divider is used).

It's helpful for odd frequencies like 20 MHz,
which can't be properly divided.

Also, it may os useful in emergency situations.
The 16 MHz crystal (quartz) is no active oscillator with a square wave output. It's just a crystal.

If it oscillates, the output will be pure sine first of all.
It's up to the chipset to form a complete oscillator circuit out of it.
Several filter or amplifier stages will turn it into a TTL/square wave signal.

That's maybe helpful in providing a stable timing signal for the ISA bus, like in case the main oscillator is unstable.
(Bus noise is an not to underestimate enemy to stability, also.)

"Clock Signals
The SCAMP Controller supports
systems with operating frequencies up
to 25 MHz. The processor clock, CLK2,
is connected to the CPU, the coproces-
sor, and other on-board logic for syn-
chronization. It is derived from the
input signal TCLK2 which is connected
to a crystal oscillator of frequency twice
the operating frequency. The frequency
of CLK2 is programmable. The bits
CLK2DIV1 and CLK2DIVO of the Clock
Control Register, CLKCTL, select CLK2
to be TCLK2, TCLK2/2, TCLK2/3, or
TCLK2/4"

..

"OSC is the buffered input of the
external 14.318 MHz oscillator.

The bus clock, BUSOSC, is supplied
from an external oscillator and is used
for asynchronous AT bus operations.

The system clock output, SYSCLK, is a
programmable clock. It is generated
from either TCLK2 or BUSOSC as
explained in the section "Programmable
AT Bus Clock". The bus control outputs
BALE, -IOR, -IOW, -MEMR, and
-MEMW are synchronized to SYSCLK."

Edit: You can check SETUP if there's a separate 8.33MHz entry in the Bus speed setting.
If it has the 8.33MHz entry in addition to CLK/2, CLK/3, CLK4 etc. it's making use of the 16 MHz crystal for sure (if 8.33 MHz is selected).

Edit: I could be wrong, but I think the manual says that TCLK2 is the 4 pin TTL oscillator and BUSOSC is 16 MHz crystal. SYSCLK is the actual frequency the system (motherboard) is running at.
CLK2 is the pin the 80386 uses for its input.

So the motherboard has the ability to use the 16 MHz in case of emergency, if the main oscillator fails.
It does some auto-detection of the BUSOSC pin during power up.
The pin can have three purposes/states: set high, set low and oscillator input.
So if the pin is put to ground/power, it acts like as switch. Otherwise, it's measuring the oscillator. That successes, if it is wired to it.

Edit: Edited.

Edit: This is also both interesting and strange.
The 16 MHz crystal is also used to accelerate DRAM access to video memory?

"CLOCK GENERATOR
The clock generator logic generates
programmable frequency clock signals.
The SCAMP Controller has a unique
expanded clock feature by which the
clock is automatically increased when
video DRAM address range, AOOOOh-
BFFFFh, is accessed. The logic
diagram of the clock generator is shown
in Figure 15.

The external input pins related to the
clock generation are TCLK2, OSC, and
BUSOSC. The output pins are CLK2
and SYSCLK."

Again thanks to all of you.
I just started to collect necessary tools as amibcp14, ctcm etc. Will try this today and come back with updates.

I will also dive a bit more into the programmable AT clock feature. So far I understood that forcing the chip to use the external osci could lead to a success.

Edit: no 8,33mhz option selectable anywhere in AMI BIOS 7/7/91

Wait, did you find amibcp14?

The option to control the ISA frequency will probably be listed as ATCLK: CLK2/8....etc. It definitely won't report the operating speed.

As I understood it is part of the zip of Herbert’s collection I found here. I add it again here. Oils not check the zip yet

It's not in there, and I don't think you're ever going to find it. It's MIA.

Damn it

As I see that all Lager versions don’t support my chipset (I will try anyway):
Do you have any further idea of how to adjust at clock? What about that hint with ctcm debug? What to do there?

From HW perspective there definitely seems a way - thanks again for the pdf link of the chipset:

The frequency of synchronous SYSCLK can be varied from 5 MHz to 25 MHz using the BUSOSC pin and the CLKCTL Register. Thus, different SYSCLK frequencies can be used for different peripheral accesses.

I fount this logic chart in the pdf. So to 50% clear but the modification - at least hardware based - is still mysterious to me. A SW-based solution would be great but i really doubt that. Assume all is triggered HW-signal based.

you are in luck chipset documentation is available. TABLE 23. INDEXED CONFIGURATION REGISTERS MAP is quite clear
ECh(R/W) Index Port
EDh (R/W) Data Port
07h (R/W) CLKCTL

1mov	AL, 7
2out	ECh, AL
3in	AL, EDh

should give you current divider config CLKCTL in AL

speechless! Thanks a lot.
My assembler skills are almost forgotten and I really hate to ask such questions so pls excuse:

- Where do I have to execute these register operations? (tool? how exactly)?
just using "debug filenamenew.exe" and then add your listed commands?

Thanks again

using debug.exe
I have no idea how tho 😀 but there are tutorials if you google around
https://jakash3.wordpress.com/2010/02/08/debug-exe-tutorial/ Assemble Command

Crazy. I checked again today in detail all:

1. without that external 16Mhz system won’t boot
2. I checked with vidspeed L instead of vidspeed * and further other video throughput benchmarks.
Result: THAT IS THE OSCI. Thruput raised by 40%.
So result achieved.

Thanks all!!

I will btw anyway continue on the assembler thing.

Br

So what did you put in the place of the 16MHz oscillator? A 20MHz part?

I put at first a 20MHz one. Now a 24MHz.
At the moment going through Phil’s bench collection. I will post results.

Results: disappointing. It’s like overclocking pci for a p60.

3dmark: 8,4 —> 8,7
Pcpbench vga: 1,8 —> 1,9
Doom: 5886 —> 5750

It’s really like nothing. Only the theoretical video throughputs show the 50% difference. But the cpu is simply too slow to stress ISA. Maybe if time I will at least see a difference for hdd performance.

Next week I will put back in my 60MHz CPU osci. Maybe more than.

THANKS TO ALL. SO MICH APPRECIATE YOUR HELP.
If time I I’ll continue with the debug

So obviously your board is operating in asynchronous mode, using the 16MHz dedicated oscillator for ISA. Possibily you get better performance by reconfiguring ISA from OSCI/1 (12 MHz with a 24Mhz oscillator) to CLK2/2 (12.5 MHz at 50 MHz CPU clock oscillator) in synchronous mode. On the other hand, it is quite likely that the ISA bus only is a significant bottleneck in dedicated video speed benches, just as you already guessed.

I will give instructions on how to switch the ISA clock using debug later.

Thanks. Looking forward to your follow up. Side remark: without the 16Mhz osci the system won’t pass the memory check but simply holds in the middle of it . Thus the board could be soldiered that way that you do require an external osci since other IC inputs won’t provide the signals you need for clk/2 operations.

Just a remark. Anyway pls continue with your feedback 😀

in the middle means you get video means there is ISA clock present, so it most likely defaults to a divider low enough to be too fast for the computer and it (being VGA) hangs

Pls excuse myself. I did not get your message. What do you mean?

Marco wrote on 2022-10-08, 18:43:

Thanks. Looking forward to your follow up. Side remark: without the 16Mhz osci the system won’t pass the memory check but simply holds in the middle of it . Thus the board could be soldiered that way that you do require an external osci since other IC inputs won’t provide the signals you need for clk/2 operations.

The SCAMP is more convoluted than I expected. I now read the datasheet and understood how it is supposed to work: It automatically detects whether the BUSOSC (16MHz on your board) oscillator is present. If yes, this oscillator is used as clock source for the ISA bus ("asynchronous mode"). If the BUSOSC oscillator is missing, the chipset automatically switches into synchronous mode, and uses the primary oscillator (50 MHz on your board) as source for the ISA bus. After the decision which clock to use, there is a divider that divides the selected clock frequency by 2, 4, 6 or 8. Actually, there are two dividers: One for ISA video memory access (or other fast cards on the ISA bus) and a second one for normal ISA operation. When you remove the BUSOSC oscillator, the pin that was used for BUSOSC instead becomes a divider selector pin. If that pin is high, the divider for "fast ISA cards like video memory" is used. If that pin is low, the divider for "standard ISA operation" is used. When you don't do anything, that pin defaults to high (the datasheet mentions an "internal pullup"). The "fast divider" defaults to a safe /6, whereas the "standard divider" defaults to a value provided by on-board bootstrapping resistors. Both dividers can be reprogrammed by the BIOS. I'm afraid that's what happens on your board:

The BIOS assumes the 16MHz clock is present and during POST, it reprograms the dividers (both the "fast" and the "standard" one) to /2. If you don't have the 16MHz oscillator installed, the pullup selects the "fast divider", which defaults to /6. So at power on, the ISA clock is 50MHz/6 = 8.33 MHz. As soon as the BIOS reporgrams the divider, it jumps up to yield a 25MHz ISA clock, which will make the system crash a short time after applying this overly high clock.

So I am sure that you need to remove the 16MHz oscillator to switch the chipset into synchronous operation (you can't do it in software, e.g. using debug), and at the same time, and I guess that you have to use a different BIOS that doesn't program the chipset to /2 operation. You can't go synchronous just by doing something in DOS after you booted with the 16MHz oscillator installed.