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VIA C3/C7 Discussion

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Reply 40 of 49, by kool kitty89

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feipoa wrote:

Yes, I am referring to a C3 Nehemiah in the CPGA form-factor.
http://www.chipdb.org/img-cyrix-via-c3-1.2aghz-2311.htm

A bit off topic, but on the note of the ceramic package: it's a bit odd having (close to) the lowest-cost/lowest-performance new processor at the time using a relatively expensive (or expensive-looking) package (not just ceramic, but the rather showy gold plated heatspreader as well). I suppose the use of ceramic could have been a patent royalty issue (which would explain why Intel alone had PPGA for so long -and why AMD implemented "OPGA" rather than PPGA), though that wouldn't explain the use of the added showy fluff of the heatspreader rather than plain ceramic packaging. (be it flat top or a plain exposed die or small/cheap heatspreader if flip-chip)

Then again, the same could be said for the 6x86/MII's rather flashy packaging compared to Intel and AMD. (or equal to Intel and AMD early-on with the contemporary gold-top packages) The black-top Cyrix chips weren't like that, of course (and actually look a bit cheaper than the K6's packaging in some respects -though overall similar thin ceramic FC-PGA), but a huge portion of late-gen Cyrix chips seem to be the traditional flashy gold-top parts with big, thick heatspreaders and thick ceramic.

Reply 41 of 49, by kool kitty89

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I noticed this thread: Cyrix III (i.e. VIA C3) for vintage gaming?
mentioned the earlier (Samuel/Ezra) C3 parts actually having the FPU running at 1/2 the core clock speed. That would at least partially explain the exceptionally poor FPU performance, though assuming the FPU itself is derived (or similar to) the old Winchip one, that was already significantly worse than the 5x86/6x86 FPU too. (and only slightly better than a 486 FPU at the same clock rate)

Reply 42 of 49, by noshutdown

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kool kitty89 wrote:

I noticed this thread: Cyrix III (i.e. VIA C3) for vintage gaming?
mentioned the earlier (Samuel/Ezra) C3 parts actually having the FPU running at 1/2 the core clock speed. That would at least partially explain the exceptionally poor FPU performance, though assuming the FPU itself is derived (or similar to) the old Winchip one, that was already significantly worse than the 5x86/6x86 FPU too. (and only slightly better than a 486 FPU at the same clock rate)

fpu running at half speed is not a good explanation for poor fpu performance, because the nehemiah core, which has full speed fpu, is only about 10% faster than previous half-speed-fpu cores in superpi.

nehemiah-1g ~9min
ezra-1g ~10min
idt c6-250 ~13min
p55c-300 ~7min

and while idt c6's fpu performance is slower than intel and amd's, the gap isn't that great at all.

Reply 43 of 49, by swaaye

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This is where we look up the programming manual for VIA CPUs. Those manuals usually describe which instructions were decided to be unimportant overall and reduced in performance.

An interesting topic to consider is Pentium 4. Intel did the a lot of the same things Cyrix/Centaur did, in order to make a CPU more about clock speed headroom than instructions per clock. Pentium 4's x87 FPU is quite weak, for example. Unfortunately Centaur and Cyrix CPUs clock low and have low IPC.

Reply 44 of 49, by kool kitty89

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noshutdown wrote:
fpu running at half speed is not a good explanation for poor fpu performance, because the nehemiah core, which has full speed fp […]
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fpu running at half speed is not a good explanation for poor fpu performance, because the nehemiah core, which has full speed fpu, is only about 10% faster than previous half-speed-fpu cores in superpi.

nehemiah-1g ~9min
ezra-1g ~10min
idt c6-250 ~13min
p55c-300 ~7min

I wasn't sure how to interpret figures for the Nehemiah given the motherboard-matching issues mentioned above. (unless those are already best-case figures)

and while idt c6's fpu performance is slower than intel and amd's, the gap isn't that great at all.

From the benchmarks I've seen, the gap is pretty big (3DNow! aside), almost on 486 levels and noticeably below the 6x86. (though certainly much closer clock for clock than the C3 appears to be)

Of course, comparisons will be benchmark dependent too, and there's a lot of variables to consider there. (benchmarks using code that focuses more on certain instructions than other benchmarks or code that performs particularly well on a specific architecture but disproportionally on other CPUs)

On the issue of FPUs, the K5 is one chip that seems to have very mixed benchmark figures for the FPU. (I've seen claims that it's faster than the 6x86, but most benchmarks show it much lower than the 6x86 at the same clock rate -I haven't seem specific cycle time figures for different operations, so perhaps it has an advantage in some areas but not others -if mult and/or add is fast, but div is especially slow, that could throw things way off, especially since the Cyrix is relatively fast at div and relatively slow at add and mult -by Pentium standards)

swaaye wrote:

An interesting topic to consider is Pentium 4. Intel did the a lot of the same things Cyrix/Centaur did, in order to make a CPU more about clock speed headroom than instructions per clock. Pentium 4's x87 FPU is quite weak, for example. Unfortunately Centaur and Cyrix CPUs clock low and have low IPC.

The pentium 4 had other design trade-offs though . . . and the Centaur design was kept simple for cost/power reasons rather than clock speeds (the C6 did the same, but scaled poorly), other design aspects of the C3 certainly focused more on clock speed scalability though (the long pipeline being an obvious one, especially compared to the 4-stage C6).

And the P4 obviously still has a much higher IPC rate than the C3 (or C6 for that matter) for both integer and floating point. (and per-clock, the FPU is still not that far off from the Athlon or PII/III FPUs -well ahead of the old 6x86 one and faster in some respects than the K6 FPU)

But, in any case, you're right about the C3's (relatively) poor clock speed scaling keeping it from being really useful in some respects (compared to the P4), and unlike the P4, it wasn't hindered by heat issues but just core stability. (and with the low IPC rate and only modest clock rates for the time, it also lost much of the perceived advantage over the Cyrix M2 based parts VIA was also considering -aside from the clock-speed marketing related issues)

Reply 45 of 49, by noshutdown

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just to my impression, the p5 generation cpus' fpu performance ranking is in this order:

p55c>p54c>k5>k6-2/3>k6>>rise mp6>idt c6>6x86(cyrix)>>via c3(not really a p5 gen though)

of course i am talking about clock to clock

Reply 46 of 49, by sliderider

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"other design aspects of the C3 certainly focused more on clock speed scalability though (the long pipeline being an obvious one, especially compared to the 4-stage C6). "

I can remember that IBM/Motorola went through similar troubles with the G3/G4 chips where up to a certain point the shorter pipeline of the original design was getting in the way of them increasing the clock speed so they had to increase the length of the pipeline in order to get the design to scale up further. At the slower end of the spectrum, the new chips were nothing to write home about compared to the prior generation, it wasn't until clock speeds got considerably faster that the longer pipeline design really showed what it could do.

Reply 47 of 49, by swaaye

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I've never seen one, but I wonder how similar WinChip 3 is to VIA C3. W3 doesn't hit anywhere near the same clock speeds though.

Reply 48 of 49, by kool kitty89

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swaaye wrote:

I've never seen one, but I wonder how similar WinChip 3 is to VIA C3. W3 doesn't hit anywhere near the same clock speeds though.

I'd gotten the impression that the Winchip 3 was a more direct extension to the previous Winchip designs with the same 4-stage integer pipleine as those chips. (the C3 being based on the Winchip 4 -or nearly identical to that except for the switch to Socket 370)

noshutdown wrote:

just to my impression, the p5 generation cpus' fpu performance ranking is in this order:

p55c>p54c>k5>k6-2/3>k6>>rise mp6>idt c6>6x86(cyrix)>>via c3(not really a p5 gen though)

of course i am talking about clock to clock

Huh. What sort of comparisons/benchmarks did you use to compare?
Any real-world applications with significant integer or I/O bottlenecks (even with heavy FPU usage as well) could still favor a chip with a weaker FPU. (I know Quake runs faster on the K5 than the K6 of the same clock rate, but that doesn't mean the FPU is stronger -the K5's per-clock integer performance is so exceptionally fast that there's huge potential for that to skew real-world application performance)

And then there's still problems with using raw synthetic benchmarks as well as those don't always reflect real-world circumstances either. (ideally, you'd want to compare things by measuring floating-point throughput of a variety of real-world applications -though hard tech info on execution cycle times and latency for various operations is even more useful for a direct comparison in some respects -in the latter case you can clearly see what operations are faster or slower in each architecture)

In the case of the 133 MHz comparison here on vogons:
133 MHz Challenge - 5th/6th gen CPU per clock performance

Shows relatively low whetsone scores for both the K5 and Winchip 2 (and outstanding integer performance on the K5), though the FPU performance in the Sandra multimedia benchmark (where most CPUs scored significantly lower than whetstone) is exceptional on the K5 (higher than the P55C, but lower than the P6) in this example. (unfortunately, no Cyrix CPUs were compared there, but similar benchmarks seem to have it similarly proportional in FPU performance in Multimedia and Whetstone -with the latter much higher than the former)

Reply 49 of 49, by feipoa

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Same Speedsys image as before at 1200 MHz, except now I'm using CL2 PC133 RAM, as opposed to CL3 PC133 RAM. The score jumped 11 points and the average memory throughput jumped by 29 MB/s.

I've also upgraded the graphics card to an Nvidia GeForce 6200LE. The 6200LE came DOA, but I replaced a few bulging caps and it worked fine. My Nehemiah system is now complete and ready for storage!

Plan your life wisely, you'll be dead before you know it.