F2bnp wrote:

So, do you guys think that maybe Intel meant for the Pentium 4 to be a stop-gap product, with an Itanium compatible desktop design coming up after a few years?

Yeah, I believe that's true as well. When I was a graduate student taking superscalar processor design, the talk was that the penalty for incorrect branch prediction was too great on the existing architecture (NetBurst) to move forward without other significant microarchitectural advancements to compensate for these pipeline flushes.

So the buzzword was "VLIW" or Very Long Intstruction Word. One of Itanium's goals was to make the processor simpler by outsourcing parallelism from the processor (implicit or derived parallelism) to the compiler (explicit parallelism). If the compiler could optimize the code and explicitly predetermine the parallelism, it would be able to pack the optimized instructions in these VLIW instructions. Simpler, faster processors... more intelligent compilers that optimize for exposed hardware parallelism at compile time instead of the processor at run-time.

This talk was happening in the late 90's before Willamette was even officially released yet. So they already knew and were working on Itanium at that point.

edit: typo

QBiN wrote:

This talk was happening in the late 90's before Willamette was even officially released yet. So they already new and were working on Itanium at that point.

Itanium was a cooperation between HP and Intel though. HP had already done quite a bit of work on the new chip (they wanted a successor to their PA-RISC line) before Intel even got involved. Itanium can be traced back to the late 80s.