Deunan wrote on 2024-04-19, 18:36:

That's expected in a system with no ISA cards, and in general these signals are rarely used. Both should be H and they are. RESE […]
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tsalat wrote on 2024-04-19, 17:31:

IO CH RDY and IO CH CK are looking the same

That's expected in a system with no ISA cards, and in general these signals are rarely used. Both should be H and they are. RESET is noisy but held L and well below 0,8V so in spec. Everything else seems in spec. MEMR appears dead but it can't be, the other lines toggling mean there is a program executing. I guess you run this with cache chips populated? In which case there might not be memory fetches if the cache always hits. CLK looks odd but it could be either triggering issue or some clock streching to hide memory refresh maybe. Hard to tell from one photo.

The F245 is used here to drive the upper address bits, the 16-bit ISA slot extension works a bit differently. But as I've said you don't need to worry about that now, we want to get the 8-bit part of the slot working first.

I did notice you changing the trigger level on some signals, please don't do that. You are only capturing the ringing noise and it's hard to tell from the photo if there are any actual logic transitions. In fact I now that I look at your earlier report about the address signals I see the same thing so now I'm not so sure that all the bits flip or not. There is one photo that shows only noise and no state changes. So please re-test the ADR00 to ADR19 lines again, no need to photo everything. If you see something like on photos 1,2 and 4 then it's OK. But photo 3 is an example of inactivity that should not really happen during normal operation. The code might just be in such a loop that a particular address line will not change but's that's unusual so write all those down if you see it.

thank you for your answer, sorry for the OSC changes, I have used the auto function and thus it resulted in it.
I have checked the Adr00 - Adr19 signals once more, screens below. The Adrxx is from a pin between the Adr19-10 (not sure which one), but most of the pins toggling between the noise and signal. Some more, some less, i.e. the noise is present most of the time with a signal appearing for a moment.

- yes, the cache is populated, not all slots but half of them

tomas

tsalat wrote on 2024-04-19, 19:02:

I have checked the Adr00 - Adr19 signals once more, screens below. The Adrxx is from a pin between the Adr19-10 (not sure which one), but most of the pins toggling between the noise and signal. Some more, some less, i.e. the noise is present most of the time with a signal appearing for a moment.

Well that's what you need to be sure of. You say that most of the pins are toggling but you need to check if all of them are. That is, there might be some noise but each and every of the ADR00 to ADR19 pins must show some activity. More or less is not very important, just that none of them is stuck at one level with no activity.

BTW can you attach a file with the BIOS image you are using?

Deunan wrote on 2024-04-19, 22:07:

tsalat wrote on 2024-04-19, 19:02:

I have checked the Adr00 - Adr19 signals once more, screens below. The Adrxx is from a pin between the Adr19-10 (not sure which one), but most of the pins toggling between the noise and signal. Some more, some less, i.e. the noise is present most of the time with a signal appearing for a moment.

Well that's what you need to be sure of. You say that most of the pins are toggling but you need to check if all of them are. That is, there might be some noise but each and every of the ADR00 to ADR19 pins must show some activity. More or less is not very important, just that none of them is stuck at one level with no activity.

BTW can you attach a file with the BIOS image you are using?

hi, sorry this is my bad, honestly now I am not sure about if I can consider the Adr stuck or toggling looking at some, and thus I made a video of it just in case.
Adr00 - https://www.sylex.repository.3d-sphere.com/in … nHyQAERtpnWcE3J (this seems to be alive)
Adr14 - https://www.sylex.repository.3d-sphere.com/in … Hyt8seKXjMC3nBp (most of the time noise but with the beep some spikes are noticeable and for a moment some signal appears)

if both videos are showing activity, all Adrxx are having something on them. Still learning so sorry for the repeated work here.
BIOS attached.

tomas

tsalat wrote on 2024-04-20, 06:51:

hi, sorry this is my bad, honestly now I am not sure about if I can consider the Adr stuck or toggling looking at some, and thus I made a video of it just in case.

There is obvious activity on the first video, and just some brief one on the second. Your problems are related to how you are using your scope, the "auto setup" button is not supposed to be used as primary measuring method. It's only there to find the signal level and maybe guess the frequency. You will have to do a proper manual tweak of settings. If you are unfamiliar with this scope, or scopes in general, there's plenty of YT videos. Not all of them are great but find one you can follow.

In short you should not be using auto triggering when hunting for signals that don't change often, all you will see is a flat line and it's easy to blink and miss all the action. Normal triggering and single triggering is there to help you. Since you are looking at 5V logic you can also set the trigger level somewhere at half so about 2.5V - and not change that. This is not correct for TTL but well-behaved circuits will trigger the scope properly so no need to dwell into differences between TTL and CMOS now.

Anyway, assuming all the address lines show at least the kind of activity as on the second video would mean none are stuck. So it's very puzzling why there are no codes on the POST card and why the mobo doesn't run. Your BIOS does output codes, and does it very early as well (as expected). I still think you should be running all these tests with the cache chips removed. You are only adding one more unknown variable by keeping them and making your life more difficult for no reason.

I've attached another "BIOS" image to program into EPROM/FLASH and try. The difference is this one does it in a loop, rather than stopping, in case your POST card or mobo is not catching the very early writes to ISA. Be sure to try it out without cache chips and also test the MEMR (B12) ISA line again, it should be toggling a lot now. This is also a good example in which address lines ADR04 to ADR19 should not change, all should be stuck at H level with no activity. Please confirm that.

If the ISA lines behave correctly but there are no codes then perhaps your mobo chips does it's own address masking for some reason, try POST2 "BIOS" then. It actually does a long jump required by x86 CPUs to unlock address bus before using I/O space. This one though has no loop, it stops the CPU right after output to POST card. Again this is a good opportunity to make sure all ISA lines (except clocks) are dead now. Nothing should be toggling after CPU is stopped, there shouldn't be even RAM refresh yet so if you do see any activity with POST2 please report it.

A small update, I've been wondering if this mobo can properly detect lack of cache installed, since there is no setting for no cache. So I looked at the manuals available on the net and compared the jumpers, and chips, with your photo - and nothing makes sense.

So on your photo the chips are installed interleaved (1 socket populated, 1 socket empty) but the manuals don't allow that. You have enough chips to get 128k of cache so you should have bank 0 fully populated, and bank 1 empty. Bank 0 is the 4 sockets in the corner. And the last 5th chip is the tag RAM, this one should go right next to the 50MHz crystal, this one is actually properly installed already.

Then there are jumpers J10 to J13, on the right side of the CPU. I can't quite tell from the photo but it seems 3 are there but not properly installed and 1 is missing completly. Please check that too. For 128k you should have 2-3, 2-3, 1-2, and 2-3 jumpered.

This is important because if the mobo can't disable cache then it will always try to access it and get glitched data, which would nicely explain why nothing works properly. So forget removing the chips, first check if eveything is installed correctly.

EDIT: Wait, this silly mobo requires two TAG chips, even for 128k. So you don't have enough installed. Both sockets next to the crystal need a chip in them. So if you don't have another 15ns '256-class SRAM chip you'll need to obtain one first.

Deunan wrote on 2024-04-20, 14:24:

A small update, I've been wondering if this mobo can properly detect lack of cache installed, since there is no setting for no c […]
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A small update, I've been wondering if this mobo can properly detect lack of cache installed, since there is no setting for no cache. So I looked at the manuals available on the net and compared the jumpers, and chips, with your photo - and nothing makes sense.

So on your photo the chips are installed interleaved (1 socket populated, 1 socket empty) but the manuals don't allow that. You have enough chips to get 128k of cache so you should have bank 0 fully populated, and bank 1 empty. Bank 0 is the 4 sockets in the corner. And the last 5th chip is the tag RAM, this one should go right next to the 50MHz crystal, this one is actually properly installed already.

Then there are jumpers J10 to J13, on the right side of the CPU. I can't quite tell from the photo but it seems 3 are there but not properly installed and 1 is missing completly. Please check that too. For 128k you should have 2-3, 2-3, 1-2, and 2-3 jumpered.

This is important because if the mobo can't disable cache then it will always try to access it and get glitched data, which would nicely explain why nothing works properly. So forget removing the chips, first check if eveything is installed correctly.

EDIT: Wait, this silly mobo requires two TAG chips, even for 128k. So you don't have enough installed. Both sockets next to the crystal need a chip in them. So if you don't have another 15ns '256-class SRAM chip you'll need to obtain one first.

hi, well, the cache settings. Apparently there are two versions of this board, at least, the P E M - 0 0 3 6 Y ( S ) and P E M - 0 0 3 6 Y. Retroweb has two jumper settings with those names in the header. My board has a print stating that BANK 0 is U1, U3, U8 and U10 wich TAG in U6 (https://theretroweb.com/motherboard/manual/pe … b1318351357.pdf). Like this the board camed, with the zig-zag configuration, however, no jumper in J10-J13. The settings you have mentioned (https://theretroweb.com/motherboard/manual/31607.pdf) are not corresponding with the print on the board and the location of BANK 0. However, I have tested both with extra cache from different board, and with different cache ICs instead the ones there are there now (took them from the board that I have by accident shorted - Re: PCChips M601 ver. 1.3B - problem (no post/ no beep) (before the short it seemed to boot up so I suppose the cache ICs are fine, although still a risk that they are wrong as well).

The behaviour with different settings I have noticed is by the beep (I was not doing extensive measurement for now with the scope) but:

- with settings according to the zig-zag manual and respective jumper settings according to the manual the beeps are continuos but with longer pause
- with no jumpers but with the zig-zag settings the beeps are continuos but with shorter pause
- with the extra cache IC and the second settings with BANK 0 in one location and the respective jumper settings according to the manual, beeps are continuos but with longer pause

In this case I would follow the print on the motherboard and thus the zig-zag location of the cache and respective jumper settings - https://theretroweb.com/motherboard/manual/pe … b1318351357.pdf

br, tomas

Deunan wrote on 2024-04-20, 12:03:

There is obvious activity on the first video, and just some brief one on the second. Your problems are related to how you are us […]
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tsalat wrote on 2024-04-20, 06:51:

hi, sorry this is my bad, honestly now I am not sure about if I can consider the Adr stuck or toggling looking at some, and thus I made a video of it just in case.

There is obvious activity on the first video, and just some brief one on the second. Your problems are related to how you are using your scope, the "auto setup" button is not supposed to be used as primary measuring method. It's only there to find the signal level and maybe guess the frequency. You will have to do a proper manual tweak of settings. If you are unfamiliar with this scope, or scopes in general, there's plenty of YT videos. Not all of them are great but find one you can follow.

In short you should not be using auto triggering when hunting for signals that don't change often, all you will see is a flat line and it's easy to blink and miss all the action. Normal triggering and single triggering is there to help you. Since you are looking at 5V logic you can also set the trigger level somewhere at half so about 2.5V - and not change that. This is not correct for TTL but well-behaved circuits will trigger the scope properly so no need to dwell into differences between TTL and CMOS now.

Anyway, assuming all the address lines show at least the kind of activity as on the second video would mean none are stuck. So it's very puzzling why there are no codes on the POST card and why the mobo doesn't run. Your BIOS does output codes, and does it very early as well (as expected). I still think you should be running all these tests with the cache chips removed. You are only adding one more unknown variable by keeping them and making your life more difficult for no reason.

I've attached another "BIOS" image to program into EPROM/FLASH and try. The difference is this one does it in a loop, rather than stopping, in case your POST card or mobo is not catching the very early writes to ISA. Be sure to try it out without cache chips and also test the MEMR (B12) ISA line again, it should be toggling a lot now. This is also a good example in which address lines ADR04 to ADR19 should not change, all should be stuck at H level with no activity. Please confirm that.

If the ISA lines behave correctly but there are no codes then perhaps your mobo chips does it's own address masking for some reason, try POST2 "BIOS" then. It actually does a long jump required by x86 CPUs to unlock address bus before using I/O space. This one though has no loop, it stops the CPU right after output to POST card. Again this is a good opportunity to make sure all ISA lines (except clocks) are dead now. Nothing should be toggling after CPU is stopped, there shouldn't be even RAM refresh yet so if you do see any activity with POST2 please report it.

thank you for your patience with me, I have worked with a scope 20years ago but literally just remember how it looked like 😀. I would definitely need some training here, and therefore I am sorry in advance if there will be hard to work with me.
I have set the trigger to 5V now and followed your "to try" list.

I have tried the POST 1a with (the "right" settings) and without cache. Below the screens from all requested pins. The MEMR B1 actually looked dead to me, I have taken the same with the default BIOS as well once more.
Also, the POST2 resulted in all lines to be dead expect the CLK and OSC.

br, tomas

Deunan wrote on 2024-04-19, 22:07:

Well that's what you need to be sure of. You say that most of the pins are toggling but you need to check if all of them are. That is, there might be some noise but each and every of the ADR00 to ADR19 pins must show some activity. More or less is not very important, just that none of them is stuck at one level with no activity.

hmm would really all be flipping when we are executing narrow sliver of BIOS code?

Deunan wrote on 2024-04-20, 12:03:

perhaps your mobo chips does it's own address masking for some reason
It actually does a long jump required by x86 CPUs to unlock address bus before using I/O space

ooo something new I never heard about before 😮 <excited> Whats this all about?

tsalat wrote on 2024-04-20, 17:01:

I have set the trigger to 5V now and followed your "to try" list.

2.5V! Trigger type to Rising edge (this you got right on the screens), capture to Single mode (button in upper right of the scope).
https://www.youtube.com/watch?v=5VyotIVwRiA

What about the oscillator - have you checked it´s 50.000 MHz, not 80.000MHz?

tsalat wrote on 2024-04-20, 17:01:

I have set the trigger to 5V now and followed your "to try" list.

You need to set it to 2.5V - it doesn't have to be super precise, you only want the scope to trigger on logic transitions. Somewhere around half the logic voltage is good, but not right at 5V - this will only capture noise (if anything at all) since the signals might not even reach 5V exactly. Please retest the 1a BIOS and MEMR line activity, to make sure there really is none (again, without cache chips).

Your Rigol scope should have USB port on the front - if you insert USB flash stick there (make sure it uses FAT format) and press the green "Print" button it should save a screenshot of on that. This might be easier for you than making photos. But the filenames are just counted up so you'll have to keep track of the pictures in your head, or just move the files to PC more often before you forget which is which. At least that's what I do.
You don't have to take pictures of everything. If you see logic activity just write down the singal name and move to the next one. But if there are doubts or you capture something you think shouldn't be there then please attach the picture.

Anyway, during that MEMR check on test 1a please also check IOR and IOW. You should see activity on IOW but not IOR. Also check adress lines as well. This is important because without codes on POST card we need another way to figure out what the CPU is doing. It seems to execute some code (since you get beeps with the BIOS, and POST2 test did stop the CPU) but not everything works properly. Problems like these are best resolved with logic analyzers but we have a scope, and that is the next best thing. We just need to be sure about the measurements, otherwise the conclusions will be wrong. So take your time, don't rush.

Deunan wrote on 2024-04-20, 22:02:

You need to set it to 2.5V - it doesn't have to be super precise, you only want the scope to trigger on logic transitions. Somew […]
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tsalat wrote on 2024-04-20, 17:01:

I have set the trigger to 5V now and followed your "to try" list.

You need to set it to 2.5V - it doesn't have to be super precise, you only want the scope to trigger on logic transitions. Somewhere around half the logic voltage is good, but not right at 5V - this will only capture noise (if anything at all) since the signals might not even reach 5V exactly. Please retest the 1a BIOS and MEMR line activity, to make sure there really is none (again, without cache chips).

Your Rigol scope should have USB port on the front - if you insert USB flash stick there (make sure it uses FAT format) and press the green "Print" button it should save a screenshot of on that. This might be easier for you than making photos. But the filenames are just counted up so you'll have to keep track of the pictures in your head, or just move the files to PC more often before you forget which is which. At least that's what I do.
You don't have to take pictures of everything. If you see logic activity just write down the singal name and move to the next one. But if there are doubts or you capture something you think shouldn't be there then please attach the picture.

Anyway, during that MEMR check on test 1a please also check IOR and IOW. You should see activity on IOW but not IOR. Also check adress lines as well. This is important because without codes on POST card we need another way to figure out what the CPU is doing. It seems to execute some code (since you get beeps with the BIOS, and POST2 test did stop the CPU) but not everything works properly. Problems like these are best resolved with logic analyzers but we have a scope, and that is the next best thing. We just need to be sure about the measurements, otherwise the conclusions will be wrong. So take your time, don't rush.

Understand, I have set the trigger below 5V before to pick up the signal but completely understand the 2,5V, my mistake. I know about the USB feature, just the photo was more convenient at that time.
As below, and as @majestyk pointed, the OSC is 80MHz and by my mistake I did not realize that or just pushed this away after confirming that the OSC is working. Hence, I would get a 50MHz for the i386 25MHz that I have in the socket and resume the measurements after. I will watch a few videos about the oscilloscope as well to save some time of you all 😀.

To sum this up, thank you again, all of you for the help. I have at least two more boards which are not behaving or starting at all and while the right 50MHz is on the way, I will most likely try to dig in to this as well and ask for help if I will be out of ideas. I guess it will take 1-2weeks for the OSC to arrive.

rasz_pl wrote on 2024-04-20, 19:05:

2.5V! Trigger type to Rising edge (this you got right on the screens), capture to Single mode (button in upper right of the scope).
https://www.youtube.com/watch?v=5VyotIVwRiA

Got it, thank you.

majestyk wrote on 2024-04-20, 19:35:

What about the oscillator - have you checked it´s 50.000 MHz, not 80.000MHz?

I have checked the OSC at the beginning if it is working, however, did not remember the value and I was pretty sure I read on the package 50 MHz, second check today, most likely I need glasses - damn, it is 80 MHz. I need to get a 50MHz one since I do not have a scoketed 40MHz CPU. This will take some time to get in. Thank you for pointing this out, I was not keeping enough attention to this...

tsalat wrote on 2024-04-21, 08:02:

...second check today, most likely I need glasses - damn, it is 80 MHz. I need to get a 50MHz one since I do not have a scoketed 40MHz CPU. This will take some time to get in. Thank you for pointing this out, I was not keeping enough attention to this...

I suspected that when I saw this:

7.995 MHz is 80/10 but can hardly be 14.318/2

As long as the 25MHz CPU is forced to run at 40MHz, any errors or non- / malfunctions are possible - chances are the board will work o.k. with the right Oscillator.

I'll admit it never even occurred to me that this could just be an issue of CPU being overclocked way past stable operation. And SX158 is possibly old enough to not be stable at that frequency - many later Intel chips would actually run well at 40MHz, just like AMD ones, but Intel was not interested in selling fast 386 chips when they already had 486 on the market.

Anyway, it'll be funny if it turns out all that was wrong with the mobo was the overclock.