CoffeeOne wrote on 2020-05-01, 09:09:
OK, so like in the picture, you have now 128kB cache (2 data chips too much but that should not hurt), and it works ok? As shown in the picture, you have set the cache size correctly to 128k
Is this correct?
Just to be sure. Did you set the cache size to 256kB, when you put in all 8 data chips?
Yeah, when all 8 are populated I set it to 256kb.
Going with your suggested configuration for 128kb, so the first 4 populated and the last 4 empty, plus the tag, I get no error, but Phil’s software also doesn’t detect any L2 Cache.
I don’t know enough about how those L2 cache sockets are linked, as I haven’t looked at any diagrams, however I’m guessing they are interconnected in series. I’m sure many on here know the details.
Because it’s banks 0&1, I suspect that when they aren’t populated due to the suggested manufacturers suggested layout, Cache won’t be detected as the series is broken. However if I populate those 2, or even just one, it’s seeing something but there is a physical problem with the electrical tracing on some pins causing the link to break.
I have a multi metre I can test the pins with, and bounced some questions off my father who’s an electronics technician, but even still this seems like a lot more work than I want to get into for 2 reasons. The first even if I do isolate a broken trace I can’t fix it, and two all the time I’m investing in this board, it’s still a VLB’less and PCI’less board.
Thanks for the all the suggestions however, much appreciated.