What happens if you try running the 440LX board and PII-266 at 5.0 x 66? Prior to wrapping up Klamath testing, I discovered that running the PII-266 on a VIA Apollo Pro 133 (VIA 694/596) with a 5.0 x 66 setting allows for 133 MHz with L2 cache enabled. Chkcpu claims it is running at 5.0 x 26.7, however PCI performance is identical to a 33 MHz PCI bus at 66 x 2.5, for example. The memory throughput also seems relatively agreeable with a 66 MHz FSB. Cachechk memory read for a Pentium II at (MHz)
133 is 92.7 MB/s
166 is 101 MB/s
200 is 111 MB/s
233 is 118 MB/s
266 is 124 MB/s
I have completed all benchmarks in DOS and Windows and everything checked out OK.
For historical value, I'm using an ASUS P3V4X. Tests in Chkcpu and Speedsys reveal that,
2x = 24.33 x 5.5 (L2 disabled) - 133 MHz
2.5x
3.0x
3.5x
4.0x
4.5x = Screen will not turn on
5.0x = 26.7 x 5.0 (L2 enabled) - 133 MHz
5.5x = 24.3 x 5.5 (L2 disabled) - 133 MHz
6.0x = 66.6 x 2.0 (L2 disabled) - 133 MHz
6.5x = 2.5x
7.0x = 3.0x
7.5x = 3.5x
8.0x = 4x
Due to these results, it is likely that the L2-disable phenomenon is due to a sensor on the multiplier setting rather than on the raw CPU frequency.
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