It seems that the CPUID of the PII-266 chip I am using is one stepping newer than the PII chip Swaaye used in the 133 MHz Challenge. Whereas my stepping is 0634, it looks like Swaaye's is 0633. There must be something different in the way 0634 handles the 2x request compared to 0633.

I used a first generation PII / PPRO board based on 440FX (Supermicro P6SKE). The disabled L2 cache is a common problem however and has been discussed here. I'm not sure if it is related to CPU, or to the chipset or BIOS.

I have not read of a software multiplier utility for P2. I wonder if you could do a edge connector mod with some electrical tape to set multiplier.

Does anyone have a Slot 1 VIA Apollo 133 chipset board with an unlocked PII w/CPUID 0633 or earlier?

I was only aware of 440BX boards disabling the L2 cache for slower clocked PII's. I didn't think this symptom would migrate into VIA boards. Having the multiplier jump to 5.5x and the FSB drop to 24.33 MHz is not something I have heard of before. Both Chkcpu and Speedsys indicate 5.5 x 24.33, however based on the memory and graphic results, I believe that the PCI and memory bus have remained at around 60 MHz. Perhaps these two programs are incorrectly reporting the CPU bus and multiplier when L2 is disabled...

A hardware mod like you suggest might be possible, however the show must go on.