From the book:
One very simple method of implementing a copy-back cache would be to
write every Valid line which was being replaced back into main memory,
whether or not it had actually been written to by the processor. This would
make the cache waste a considerable amount of bus bandwidth with un-
necessary main memory write cycles, due to all the evictions of lines which
had not been written to by the CPU. Another problem with this method is
that all line replacements would take twice as long as would line replacements
in a write-through cache, since write-through line replacements require
only a main memory read cycle. To avoid this burden, the cache is usually
implemented with a means to signify whether a line in cache is more
current than the main memory location it represents. The simplest method
is to use another bit for each line in the cache, and this bit is called the Dirty
bit. Data which has been written in the cache, but has not been updated in
the main memory is tagged as Dirty by the cache controller's setting this bit.
Like the Valid bit, there is usually a Dirty bit for every line in the cache (Figure 2.l4).
During a cache miss cycle, the line to be replaced is examined, and, if its
Dirty bit is set, the current contents of that cache line are evicted back into main memory.
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