Thanks Vetz for this insight. Do you had also a look on some cache / memory latency time values?

Oh and TX SDRAM is slower than TX with EDO, or is this just a CAS latency setting? (CL2 vs. x233 or what was the setting?)
Also HX is slightly faster than TX with EDO...

Sorry Elianda. Forgot to mention that in my first post. All Intel 430 FX/VX/HX/TX boards were run at the same memory latency settings as long as it was possible (many of them suggested this for 60ns EDO RAM which I used).

Basically:
Read burst 222/333
Write burst 222
R/W Leadoff 6/5 (this varied a bit in possible BIOS settings)
RAS Precharge 3
RAS to CAS Delay 2

SDRAM was run at CAS2 as everyone have PC100 or PC133 nowadays which has no problem running CAS2 at 66mhz.
I was a bit surprised of the SDRAM results. It is faster in Quake and synthetic benchmarks like Speedsys, but slower in Doom and PCPBench. I guess this is mainly due to poor SDRAM implementation on these early boards. On the MVP3 SDRAM wins pretty clear in all tests.

HX being faster than TX might be due to more PCI to memory buffers, but it might also be that my Gigabyte HX board is of better quality than my Aopen TX board. HX was though targeted towards highend machines/servers.
Comparison here: http://www.pcguide.com/ref/mbsys/chip/pop/g5i … mparison-c.html

Hmm regarding all memory timings. My testings suggest that even if you can run some memory on CL2 settings (I did test dozen pc133 512mb sticks) that doesn't mean they will be exactely fast. All of 512mb sticks that i tested on my old board were slower when runing CL2 then when
running SPD adjusted to auto settings. That got me thinking. SPDs are programed by certain factory to their specification. I had few sticks with
7ns chips. Sticks and chips ere identical but some were labeled CL3 and very little of them were labeled CL2. Those of CL3 could be run on 133mhz
FBS at CL2 settings but did score fewer point than original CL2 labeled sticks. My only explanation is that information store in SPD is what makes
them faster od slower. Same thing when overclocking; lets sad at 166mhz FSB. Original CL2 sticks will be faster than CL3 but CL3 could work on
this faster FSB just because chips are 7ns. Correct me if I'm wrong but i see no other reason why same chips got CL2 or CL3 labels on them.
I had a huge table in excel while testing memory in 3dMark,Sandra and Everest to confirm there is no match for PC 133 222-520 labels... Sorry if this is bit off !

Vetz,
Great comparison for cache design strengths of pipeline burst. I never realised pipeline burst was such a hit. At the time (1998), I went from a AMD X5-133 to a dual PII-400 and skipped over the socket 7 era. You should place your VLB POD100 system in a column in this chart just for ease of comparison. Another column for the Socket 5 P100 would be nice too.

stuntman,
Each DIMM has an onboard ROM which specifies the speeds to run the module at by default. The motherboard BIOS can overwrite these settings, though. I've read unsuccessful stories online about reprogramming the ROM's SPD values.

In some cases, just because the speed rating of the individual memory chips on the module are rated for CL2, 133 MHz, it may not mean the module will be rated for this. A particular case comes to mind with registered DIMMs, which have a phase-lock loop (PLL) on the module, i.e. CDC2510B. I've seen registered DIMMs with individual memory chips rated for CL2, 133 MHz, however the PLL on the actual module was only rated for PC100. This limitation was due to the PLL's max frequency specification of 125 MHz. Due to this, the module's ROM SPD settings were only programmed for PC100.

In reality, I found that these registered ECC PC100 chips worked fine at 133 MHz, but many OEM server boards don't let you adjust the memory timings - they go strictly off the pre-programmed SPD.

I'am still a bit surprised about the differences between the VX,HX, TX with EDO and then the performance shift with SDRAM on TX.
It seems that VX is a bit faster with EDO than TX, HX is the fastest. This is also resembled in the scores. But regarding your linked table the TX should have the shorter memory timings.
The SDRAM vs EDO on TX seems to give a higher memory speed, however I think for bad aligned code, as pcpbench and doom the higher latency of SDRAM may give a performance decrease. Quake gets a slight increase however.
It might be interesting if the behavior is the same with EDO vs SDRAM on VX. This would clear up a bit the picture, where the gains of SDRAM is on these chipsets (if any), and if the faster memory scores from benches mean anything in applications/games.

feipoa wrote:

Vetz, Great comparison for cache design strengths of pipeline burst. I never realised pipeline burst was such a hit. At the ti […]
Show full quote

Vetz,
Great comparison for cache design strengths of pipeline burst. I never realised pipeline burst was such a hit. At the time (1998), I went from a AMD X5-133 to a dual PII-400 and skipped over the socket 7 era. You should place your VLB POD100 system in a column in this chart just for ease of comparison. Another column for the Socket 5 P100 would be nice too.

stuntman,
Each DIMM has an onboard ROM which specifies the speeds to run the module at by default. The motherboard BIOS can overwrite these settings, though. I've read unsuccessful stories online about reprogramming the ROM's SPD values.

In some cases, just because the speed rating of the individual memory chips on the module are rated for CL2, 133 MHz, it may not mean the module will be rated for this. A particular case comes to mind with registered DIMMs, which have a phase-lock loop (PLL) on the module, i.e. CDC2510B. I've seen registered DIMMs with individual memory chips rated for CL2, 133 MHz, however the PLL on the actual module was only rated for PC100. This limitation was due to the PLL's max frequency specification of 125 MHz. Due to this, the module's ROM SPD settings were only programmed for PC100.

In reality, I found that these registered ECC PC100 chips worked fine at 133 MHz, but many OEM server boards don't let you adjust the memory timings - they go strictly off the pre-programmed SPD.

Agree. But I noticed every benchmark and every score to be better if SPD in BIOS was set to auto. If I manualy set it to CL2 (on real CL2 stick)
it would score worse.. It got me thinking that ROM was better programed than BIOS setting can overwrite it. Or to say, when system BIOS asks
memory for timings programed on SPD it will give better results then when you manualy set timings. I don't know whats the deal with it, but it was always on Auto.

I also have some memory about EDO RAM having lower latency while SDRAM having higher bandwith and higher clock ceiling. The numbers make some sense then if we assume Quake is bandwidth dependent. After the Doom source code was released I had a look into it and I remember that it did a lot of table lookups which would make it latency dependent.
Similar Quake 3 ran good on P4s because of the high bandwidth and Doom 3 ran better on Athlon 64 than on P4 because of the lower latency (integrated memory controller).

HX was known for having excellent EDO performance.

idspispopd wrote:

I also have some memory about EDO RAM having lower latency while SDRAM having higher bandwith and higher clock ceiling. The numbers make some sense then if we assume Quake is bandwidth dependent. After the Doom source code was released I had a look into it and I remember that it did a lot of table lookups which would make it latency dependent.
Similar Quake 3 ran good on P4s because of the high bandwidth and Doom 3 ran better on Athlon 64 than on P4 because of the lower latency (integrated memory controller).

HX was known for having excellent EDO performance.

This could explain a lot. I remember quake 3 arena benchmarks on radeon 7500 and 9800 pro gave me same results, about 130fps. System configration was the same just different graphic cards. If you are right about Quake being bandwith dependent ithen it makes sense...

How much RAM was used in the tests? The HX was a server chipset and could cache much more RAM then the VX and TX (limited to 64MB I think). For old games that's not an issue but if you like to max out a system that would be a problem.

feipoa wrote:

You should place your VLB POD100 system in a column in this chart just for ease of comparison. Another column for the Socket 5 P100 would be nice too.

I've updated the results to be more in line with what I think you want.

Unknown_K wrote:

How much RAM was used in the tests? The HX was a server chipset and could cache much more RAM then the VX and TX (limited to 64MB I think). For old games that's not an issue but if you like to max out a system that would be a problem.

32MB (2x16MB) 60ns EDO RAM was used. Within the cachable range.

stuntman wrote:

Agree. But I noticed every benchmark and every score to be better if SPD in BIOS was set to auto. If I manualy set it to CL2 (on real CL2 stick)
it would score worse.. It got me thinking that ROM was better programed than BIOS setting can overwrite it. Or to say, when system BIOS asks
memory for timings programed on SPD it will give better results then when you manualy set timings. I don't know whats the deal with it, but it was always on Auto.

There are no AUTO settings on the TX or MVP3 motherboard in the test. Only option for SDRAM is CAS 3 or CAS 2.

stuntman wrote:

idspispopd wrote:

Similar Quake 3 ran good on P4s because of the high bandwidth and Doom 3 ran better on Athlon 64 than on P4 because of the lower latency (integrated memory controller).

This could explain a lot. I remember quake 3 arena benchmarks on radeon 7500 and 9800 pro gave me same results, about 130fps. System configration was the same just different graphic cards. If you are right about Quake being bandwith dependent ithen it makes sense...

That's not exactly what I meant. In your case the benchmark was just CPU limited so a faster video card was of no use (except maybe very high resolutions or AA levels).
What I mean is that according to these benchmarks in Quake 3 a 1.3 GHz P4 Willamette beats a 1.33 GHz Athlon Thunderbird while in Unreal Tournament 2003 a 1.2 GHz Athlon beats said P4.
(Or at the higher end in Quake 3 a 2.66 GHz P4 Northwood beats an Athlon XP 3000+ Barton while in Unreal Tournament said Athlon XP is at the top beating even a 3.06 GHz P4.)

Of course this could be a result of several CPU performance characteristics, but IIRC the opinion at the time was that Q3 loved the bandwidth P4's could deliver, even though they had worse IPC.