386 motherboards with intel chipsets are pretty rare. At first glance is appears to have no cache, but when reading a PC magazine one day I learned that this chipset supposedly has 8 or 16kb built in so the performance is probably not too bad.

Thanks for the quick reply!

I explored the PC Magazine lead that you suggested and found several ads from 1992 about early 486SX PCs apparently using the same chipset (ISA only 486 😕 ). That may be where you remember reading about the integrated cache from. Those ads mention the chipset by name and advertise an integrated 8KB cache without saying that it's the 486 on-die cache.

All the 340DX chipset information that I could find said that it can be used with or without cache. Now L1 should not be present in a 386 class CPU because none of the chipset of that era would expect it and it would conflict with the chipset's own cache controller. I believe that's why the on-die cache was removed from Intel RapidCAD upgrade for 386 PCs (repackaged 486). As I remember main boards supporting both L1 on-die and L2 on-board required completely different chipsets, namely the VLB and PCI ones of later 486 PCs.

I'll find out about the cache if the thing ever posts when I'm done building it. 😀 Any idea about the various jumpers? I can guess the function of a few of them based on experience but if you can help be my guest...

Just in case the images aren't clear these are the 3 main chips on the board:
VLSI VL82C332-FC Data Buffer
Intel S82346A (aka VLSI 82346) Memory Controller
Intel S82344A (aka VLSI 82344) ISA Bus Controller

I think that I found what it is!

http://museum.ttrk.ee/th99/m/A-B/30657.htm

It's almost a perfect match however it says no cache... 😢

At least all the jumpers are explained:

JP1 Closed=Color, Open=Monochrome

Keyboard Config
JP3 Closed=Controller Select Pin 23
JP4 Closed=Controller Select Pin 24
JP5 Closed=Controller Select Pin 27
JP6 Closed=Controller Select Pin 32

JP8 1-2=80387, 2-3=Other Coprocessor

JP9 1-2=CMOS Normal, 3-4=CMOS Clear

JP10 1-2=Internal Battery, 2-3=External Battery

JP14 Closed=Pipeline Mode Enabled, Open=Pipeline Mode Disabled

Considering L1 cache, there are 486DLC chips that feature at least 1Kb L1, so there is hardly any problem with 386 chip sets not knowing about it.

I remember reading an actual article about this chipset, not an advertisement. It was probably in either a 1989 or 1990 issue. I will attempt to find the article again (I read it just two weeks ago). Failing that, I would be willing to bet the datasheets for the chipset are available.

This board probably won't support the 486DLC properly unless it has hidden refresh setting in the BIOS.

Thank you for challenging my statement Racoon.

I did some additional research and you're correct, both on-die and on-board cache is possible on 386 hardware. I think that what got me confused is that all such solutions end up using two distinct cache controllers, the one within the CPU and the one within the chipset. I'm used to more modern hardware having only one cache controller for L1, L2 and L3 when applicable. I can't quite recall exactly what it was that lead me to think that it wasn't possible at all but somehow I still feel that redundant cache controllers can lead to cache incoherence if they aren't completely hidden from each others which is in turn considerably sub-optimal.

I found the Intel's 1990 386 System Design Considerations. The problem seem to be that the 340DX chipset needs an external cache controller as it lacks one! Intel suggests pairing it to the i385 or i395 cache controllers however any other similar product would do in which case the whole chipset becomes a 4-chip solution (Memory controller, memory buffer, cache controller and ISA or EISA bus controller) which seem to have been reserved for the then top-of-the-line systems.

pdf.datasheetcatalog.com/datasheet/Intel/mXtuvqv.pdf

90sToys,

Never knew your board was so old 😀 I recall seeing an i385 in huge top-end 386 boards, just as you say, but yours looks more modern.

90sToys wrote:

I did some additional research and you're correct, both on-die and on-board cache is possible on 386 hardware. I think that what got me confused is that all such solutions end up using two distinct cache controllers, the one within the CPU and the one within the chipset.

Actually this only changed with Pentium Pro and Athlon (K6-3 had L1 and L2, but the MB usually still had it's own cache which in that case became L3 instead of L2).

Found the chipset datasheet!

I can't see anything that either says that there is or isn't integrated cache in there. I guess that I'm back to square one, I'll have to boot the thing to see if it has any form of integrated cache. We'll soon see... 😎

Biostar MB-1325VT/1333VT (VER. 2)
http://www.win3x.org/uh19/motherboard/show/1063