First post, by meisterister
- Rank
- Newbie
Since we're busily living in the future, I'd like to give a bit of an elevator pitch for an idea I had:
One of the biggest difficulties with running retro hardware besides the various compatibility problems is that CPUs can sometimes be pretty hard to come by. This fact has been exasperated by the excessively high price of gold, which has driven many people to destroy otherwise perfectly functioning processors, which in turn reduces supply and increases costs for us. We currently have available to us several very well written 486-compatible cores (like this one https://github.com/alfikpl/ao486) that can readily be put onto fairly cheap and small FPGA or CPLD devices. It's possible that because of the massive improvements in manufacturing technology since the early '90s, it's possible to run these cores far faster than technology at the time would have allowed. Furthermore, due to the relatively low barriers to entry imposed by verilog and VHDL (vs. designing a state-of-the-art CPU in the early '90s), it should be possible to implement far wider and more efficient cores than a pure 486.
My idea is this: we should try to connect a modern FPGA to an older socket (like Socket 3)? The pinouts should be fairly well known, the cores are available, and the voltages used (3.3 or 5 volts) are commonly used by FPGAs to signal external devices.
The biggest challenges I can think of:
1. Getting timing and synchronization to work correctly (an FPGA board would be situated farther away than a normal CPU would, and those delays could cause instability)
2. Various chipset-based errata. (Once again, a huge problem for stability).
3. Actually doing the wiring. (While schematics and such are available, the 486 still does have an impressively large number of pins).
4. The core presented is a 486SX, and I could imagine that implementing an FPU would be terrifying.
5. It's arguably not a "real" 486.
Advantages in brief:
1. Can be widespread and future-proof (in that FPGAs and CPLDs aren't going anywhere anytime soon).
2. Can allow for (theoretically) higher clock speeds. Note: Spartan 3 boards, which are kind of a baseline, cheap part, can only really manage in the low 100s of megahertz with a good design. Inserting pipeline stages could potentially help this, but then we'd have a bit of a Pentium 4-86. Newer boards should be better.
3. Can allow for wider/more efficient cores. While doing so would be a complete PITA, it could be possible to have better FPUs, branch prediction, multiple pipelines, and other such coolness.
4. If the FPGA is big enough (this is a big sticking point), more cache could be allocated, which could allow boards with fake cache to become far more useful.
5. Can allow for updates. The CPU could be reprogrammed if a bug is found in the HDL design.
Dual Katmai Pentium III (450 and 600MHz), 512ish MB RAM, 40 GB HDD, ATI Rage 128 | K6-2 400MHz / Pentium MMX 166, 80MB RAM, ~2GB Quantum Bigfoot, Awful integrated S3 graphics.
