Wow what an interesting question, never really thought much about CPUs having there own bus. HT is classified as a form of Serial bus and a lower latency replacement for the FSB which is what I would consider the CPU bus being it communicates with pretty much everything external from the CPU. Far as I know FSB started with the first Pentiums they had a double bus in them so the CPU could have a higher bus speed/performance without affecting the other buses in the system like ISA.

QPI, HT, P4 (used in various guises for Core and Core 2 as well), V4, EV6 (Athlon)

I'm not familiar enough with the electrical characteristics of P3 busses and earlier to know what differentiates them.

For non-x86 we have AMBA, Wishbone, Ultrasparc III bus, Fireplane, Ultrasparc II bus, SGI Avalanche, SysAD, PCIe/CAPI, GX/GX+/GX++, SMBus, SBus, GSC, CoreConnect, S-100.

I know there are more, but these are the ones I knew or could find. Some could be variants of others (on the Ultrasparcs, for instance).

Pentium pro - 3 is AGTL+

And from what I can find prior to AGTL+ intel used AGTL for their FSB prior to Pentium Pro if wiki is to be belived.
https://en.wikipedia.org/wiki/Gunning_transceiver_logic

I don't think you can see ISA as *the* CPU bus for most PCs.
For the original PC/XT at 4.77 MHz that may have been true, but as faster computers arrived (even 8088/8086-class machines such as Turbo XTs), the ISA bus had to be decoupled from the CPU (and FPU), because ISA devices were never designed for the high clockspeeds that newer CPUs could run at. So the ISA bus was generally running at around 8 MHz max (running asynchronously), while the CPU, FPU and memory could run at much faster speeds on another bus.
The 486 then introduced the 'localbus' concept, where you could once again run devices on a bus at the full speed of the CPU, with lines going directly to the CPU, similar to early 8088-based PCs (basically an extension of the CPU's memory bus).
I guess the Pentium turned it all upside down again, because you'd interface the CPU to the chipset, which contained a PCI controller and a PCI-to-ISA bridge. PCI is not 'localbus' in the way it was implemented on 486. PCI was just a high-speed bus protocol, arbitrated by the chipset.

If "bus" is "the thing" that connect CPU to other things.

FSB (competitor : EV6) :
Front Side Bus, was used From Pentium Pro/Pentium II till Core 2 Quad's QX9xxx as a link to north bridge (NB) that housed Memory Controller and PCI-e/AGP controller.
It was doing "fine" until we hit 1GHz mark on CPU side at which point AMD dropped EV6 development and started doing research on something new : Hyper Transport.
Intel made FSB go ridiculously fast in mid 2000's (from [QPB] FSB 533MHz in 2002 to FSB 1600MHz in 2007), but in the end they were forced to make something new (QPI).

Hyper Transport :
Designed to connect CPU with Northbridge (where PCI-e is) OR other CPUs with HT bus (NUMA).
Vastly improved performace from FSB, combined with getting memory controller onto CPU die, made it last till now (don't know what AM4 will be using).

QPI :
Quick Path Interconnect - Intel's succesor to FSB, designed to connect chips with eachother.
Usually used in Xeon CPU's to connect them together, it's used in Clarkdale type (ie. 1-st gen i3's) chips, to connect "Core die" with "Uncore" and iGPU/IMC die.

DMI :
Till "Core i" series, Direct Media Interface was use to connect Intel's North bridge (Chipset) to South bridge. But since NB's have become pointless with LGA 1156 and later sockets, DMI is connecting CPU with now "chipset" (South Bridge of the past).

^Basic info anyone should know.

agent_x007 wrote:

Front Side Bus, was used From Pentium Pro/Pentium II till Core 2 Quad's QX9xxx as a link to north bridge (NB) that housed Memory Controller and PCI-e/AGP controller.
It was doing "fine" until we hit 1GHz mark on CPU side at which point AMD dropped EV6 development and started doing research on something new : Hyper Transport.
Intel made FSB go ridiculously fast in mid 2000's (from [QPB] FSB 533MHz in 2002 to FSB 1600MHz in 2007), but in the end they were forced to make something new (QPI).

I would say that the huge and fast caches also helped a lot with the slower buses.

Also with the off-die memory controllers.

NVidia uses HyperTransport for all their Chipset pair offers since AthlonXP days.

VIA, ALi and SiS had also their propietary technologies to connect their Chipsets, until HyperTrasport became the rule, and Intel didn't licensed 3rd party chipset makers anymore.

gdjacobs wrote:

Also with the off-die memory controllers.

This makes me wonder how current CPUs would perform with their caches disabled. According to memtest86 (which may not be accurate) the memory controllers on modern Intel CPUs provide quite a bit more bandwidth than the caches of older CPUs like the P4 and Athlon 64.

Standard Def Steve wrote:

gdjacobs wrote:

Also with the off-die memory controllers.

This makes me wonder how current CPUs would perform with their caches disabled. According to memtest86 (which may not be accurate) the memory controllers on modern Intel CPUs provide quite a bit more bandwidth than the caches of older CPUs like the P4 and Athlon 64.

Don't most modern Intel CPUs have L3 cache? This may be why, L3 cache is common memory pool available to both front side bus for external communication and the rear side bus for internal communication. This what makes the P4EE faster L3 cache takes the load off the FSB because the larger L3 pool can retain data so CPU does not have to call it externally from the memory sometimes known as the L4 cache and HDD sometimes known as the L5 cache. Also unlike L1/L2 cache which is available only to the core it is embedded into L3 cache is shared internally by multiple cores if the CPU has them, not sure if the L3 has any effect on Hyper Threading in the P4

@candle_86: Interesting find about AGTL, but I'm guessing this wouldn't be the name of the bus? It seems to be the electrical specification, like the ISA bus uses TTL? So if I understand correctly, you wouldn't call the PPro-P3 bus AGTL for the same reason you wouldn't call the 8086 bus TTL, right?

@Scali: When you say "...the CPU, FPU and memory could run at much faster speeds on another bus", how should you refer to these buses? I agree that e.g. a 20MHz 286 must be decoupled from the 8MHz ISA bus, but I'm unclear on how exactly is this done. The 286 machines I have have an oscillator that's double the CPU speed, so it makes me think the bus they use - whatever it's called - runs at double the CPU speed and effectively the CPU has a 0.5x multiplier. But finding a name for that non-ISA CPU bus eludes me for these early machines.

So what I have now, for the eras I'm interested in, are:

• 8086/8088: ISA @ 4.77MHz, ? for later turbo XT boards
• 286: ?
• 386: ? @ 12-40MHz
• 486: Maybe VLB? @ 16-50MHz
• Pentium 1: ? @ 50/60/66MHz
• Pentium Pro: FSB @ 60/66MHz
• Pentium II: FSB @ 66/100MHz
• Pentium III: FSB @ 100/133MHz

Malvineous wrote:

@candle_86: Interesting find about AGTL, but I'm guessing this wouldn't be the name of the bus? It seems to be the electrical s […]
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@candle_86: Interesting find about AGTL, but I'm guessing this wouldn't be the name of the bus? It seems to be the electrical specification, like the ISA bus uses TTL? So if I understand correctly, you wouldn't call the PPro-P3 bus AGTL for the same reason you wouldn't call the 8086 bus TTL, right?

@Scali: When you say "...the CPU, FPU and memory could run at much faster speeds on another bus", how should you refer to these buses? I agree that e.g. a 20MHz 286 must be decoupled from the 8MHz ISA bus, but I'm unclear on how exactly is this done. The 286 machines I have have an oscillator that's double the CPU speed, so it makes me think the bus they use - whatever it's called - runs at double the CPU speed and effectively the CPU has a 0.5x multiplier. But finding a name for that non-ISA CPU bus eludes me for these early machines.

So what I have now, for the eras I'm interested in, are:

• 8086/8088: ISA @ 4.77MHz, ? for later turbo XT boards
• 286: ?
• 386: ? @ 12-40MHz
• 486: Maybe VLB? @ 16-50MHz
• Pentium 1: ? @ 50/60/66MHz
• Pentium Pro: FSB @ 60/66MHz
• Pentium II: FSB @ 66/100MHz
• Pentium III: FSB @ 100/133MHz

The 8086/8088, all the way to the Pentium 4 may have an ISA bus, but on the 486/Pentium they are most certainly on a bridge chip connected to south bridge of the FSB (Front Side Bus) For all intents everything 486+ has a Front-Side Bus, but the physical CPU only communicates accross it to the bridge chips, not expansion cards. The chipset, which the North Bridge connects the RAM to the CPU, and the South Bridge connects the PCI/ISA bridge to the North Bridge.
This has a diagram: https://en.wikipedia.org/wiki/Northbridge_(computing)

The only weird "buses" on the 80x86 chips are the names the FSB go by and the link between the North Bridge and South Bridge chips. With the Sandy bridge chipsets, the northbridge was integrated into the CPU. AMD did the "integrate the memory controller" bit first. You'll see DMI(P4), QPI(Servers), and so forth. Of note, the i820 chipset is the odd man out, when Intel was attempting to force RAMBUS on the P4 generation and every single i820 MTH (to connect non RAMBUS RAM) failed.

AGTL+ is the actual electrical technology that the FSB uses, and isn't the bus name used by marketing itself. QPI is Intel's answer to HyperTransport, while previously DMI (Direct Media Interface) was the bus between the north and south bridge since 2004. For all intents, when you want to talk about computer buses, it goes "connectivity" with a port or connector eg Serial, Parallel, ISA, PCI, VLB, PCI Express, AGP, USB, Firewire, Thunderbolt. Or internal buses with protocols (eg QPI/DMI/HT.) AMD used Alpha's EV6 before Hypertransport.

Prior to the 486, you had some competing replacements for ISA. So you had ISA-PnP, EISA, and MCA which were not real improvements, just extensions or in the case of MCA, IBM trying to use it's brand as leverage to regain control over something they can license. Which in a way is ironic because that's exactly what Intel did to AMD (AMD couldn't make Pentum clones, but their 386 and 486 chips worked intel boards), and nVidia (which is why you don't see any nVidia chipsets for intel after 2008.) When AMD bought ATI in 2006, that locked nVidia completely out of the motherboard game.

Anyway, that's why on new machines you often see things like "PCI Express to PCI bridge" "PCI to PCI bridge" and "PCI to ISA Bridge" much in the same way there are bridge adapters for SATA/PATA and USB/Serial/Parallel ports.

VLB was short lived and found only on 486's. It was also the reason why PCI came out (which was also on 486's, but all Pentium systems) Because VLB operated at the FSB speed, while PCI was set at 33Mhz. At the time VLB was 66Mhz and only used as an extension of the motherboard (eg the hard drive and video card were on it) where as in PCI motherboards, the hard drive controller became integrated (I can not ever recall seeing a PCI hard drive controller since all Pentium systems seemed to have all the Super IO integrated.) Sound cards on the other hand stayed on ISA for a super-long time.

I'm not sure what the 8087/80287/80387's were connected by if they were even used (I've never seen a separate FPU chip installed on any system, the sockets were always empty.)

Malvineous wrote:

@Scali: When you say "...the CPU, FPU and memory could run at much faster speeds on another bus", how should you refer to these buses?

I'm not sure if these buses have any 'official' names. The 'high speed' link from CPU to chipset (with the memory controller) is just referred to as 'memory bus', and I suppose the FPU is connected to the 'FPU bus'.
Since these buses were only used internally, unlike the ISA bus, I guess there was no need to put some kind of marketing term on there. This marketing started to occur when AMD and Intel each moved to their own socket and bus system, and they started to compete on bus speed.

The 8087 is a special case, by the way. The 8086/8088 bus can be seen as a sort of 'superset' of the ISA bus. There are a few signals on the bus that indicate the state of the CPU in fetching and decoding instructions, and a 'handshaking' signal for the FPU to have the CPU wait until it is done (using the FWAIT instruction).
The 8087 basically 'sniffs' the bus, allowing it to know when and where the CPU is decoding instructions. The 8087 runs in parallel, and if the special byte for FPU-instructions is found, the FPU will take over. It's especially interesting, since the FPU even relies on the CPU to generate all memory addresses (addressing can be done via the CPU registers, and the FPU does not mirror these). It works by the CPU generating the address of the first byte/word of an operand on the bus. The FPU will then take this address, and increment it to fetch subsequent bytes/words on the bus.

287 and 387 newer have a dedicated bus between the CPU and FPU. One difference from a software point-of-view is that the FWAIT behaves differently (and is generally no longer required). On an 8086/8088, the FWAIT instruction just makes the CPU wait indefinitely for the signal from the FPU. If no FPU is installed, your system will lock up (this is one of the many things that emulators fail to emulate).
On a 286 or newer, FWAIT will not lock up when no FPU is installed. The instruction will just fall-through.

Another interesting thing is that the 286 runs its CPU asynchronously. Because early 287 FPUs could not scale to the same clockspeeds as the 286, they were run at 2/3 of the CPU clockspeed. The later 287XL was based on the 387SX, and could run at the same speed as the 286. To do this, they have an internal 3/2 multiplier to correct the 2/3 clockspeed from the motherboard back to the CPU's clockspeed.

Malvineous wrote:

There's not a lot of info around about CPU buses generally (only a few specific examples), so what would you consider to be the primary bus type of the common CPUs from the 8086, 286, up to Pentium 1/2/3, etc?

I would consider primary the bus which sits between the CPU and memory, the "data bus". As Scali said, they usually don't have any specific name, the exceptios are the the standardized buses between CPUs and memory controllers (like FSB and EV6).