Reply 40 of 61, by Horun
I have a few other 486 VLB boards with cache and the caps for the cache are 100nF (or 0.1uF) radial multi-layer ceramic (or Tanatalum appearing types) on both of them. They both are stamped 104 MEE from what my magnify lens shows me. So any 100nF (o.1uF) SMT cap should work.
As for cache the board excepts 32kx8, 64kx8 or 128kx8 density main cache chips. If you decide to fix it and just go for 256k total cache you are better to use 9 x 32kx8, if you use 4x 64kx8 plus one 32kx8 for TAG (still 256k) OR 4x 128kx8 plus one 32kx8 TAG (for 512k) then you have to disable the "auto" setting in BIOS cache because the AUTO defaults to interleaved using both cache banks but you will only fill one bank, also you must set Cache Read Speed to 3-2-2-2. ---> from the Archived Amptron website, the DX-6900 v1.7 is the M912 v1.7.
Best to fill both bank0 and Bank1 with cache chips just in case you loose CMOS settings and did not make a note/remember the cache setting. It will boot but hang near end of POST if cache is not set right in BIOS using just one bank.
added: attached the archived webpage zipped.
Hate posting a reply and have to edit it because it made no sense 😁 First computer was an IBM 3270 workstation with CGA monitor. 🤣 Second computer a 286 12Mhz with real IDE drive ! After that came 386, 486, Pentium, P.Pro and everything after....