VOGONS


Reply 1080 of 1247, by MikeSG

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ChrisXF wrote on 2023-11-12, 21:33:

I gave it a whizz from 33mhz to 40: that worked fine, but the moment clock doubling was switched on it hung.

There's a few lines in the manual about stability and using pullup resistors. Some mother boards may have them, some not...

I'm looking through the whole manual as I'm building my own interposer.

Page 197: (Hold acknowledge timing) Note 2 - "For maximum design flexibility the CPU has no internal pullup resistors on its outputs. External pullups may be required on ADS# and other outputs to keep them negated during hold-acknowledge period."
Page 208 (Terminals Requiring External Pullup Resistors) - "It is recommended that the ADS# and LOCK# output terminals be connected to pullup resistors, as indicated in Table 5-2. The external pullups ensure that the signals remain negated during hold-acknowledge states." Table 5-2: 20k pullup resistor for each.

Other things. This is what I derived from reading everything on pipelining:
TI486SXL Pipeline support:
a) If Pipelining is supported, and the NA# pin (active low) is driven, the CPUs NA# pin should be connected & driven by the chipset.
b) If Pipelining is supported, and the NA# pin (active low) is NOT driven, the CPUs NA# pin should not be connected and should be pulled low with a 100-ohm resistor 0.5W.
c) If Pipelining is not supported, the CPUs NA# pin should not be connected and should be pulled high with a 10k/20k resistor.
d) If Pipelining is unknown, the CPUs NA# pin may be connected and pulled high with a 20k resistor.

I have a whole section on FLUSH/MEMW as well if interested.

Reply 1081 of 1247, by ChrisXF

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That's interesting! Pull ups wouldn't be hard to do on the board I have.

The next thing I'm looking at it the flush capability: I just soldered in a connection for MEMW on ISA, and once I get the board back in a case and running I'll be looking at that.

I haven't done much with pipelining, but iirc when I enabled it with the cyrix utility it did give a speed bump.

This cpu is a rubix cube of options! 🤣

Reply 1082 of 1247, by feipoa

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MikeSG wrote on 2023-11-14, 13:11:
There's a few lines in the manual about stability and using pullup resistors. Some mother boards may have them, some not... […]
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ChrisXF wrote on 2023-11-12, 21:33:

I gave it a whizz from 33mhz to 40: that worked fine, but the moment clock doubling was switched on it hung.

There's a few lines in the manual about stability and using pullup resistors. Some mother boards may have them, some not...

I'm looking through the whole manual as I'm building my own interposer.

Page 197: (Hold acknowledge timing) Note 2 - "For maximum design flexibility the CPU has no internal pullup resistors on its outputs. External pullups may be required on ADS# and other outputs to keep them negated during hold-acknowledge period."
Page 208 (Terminals Requiring External Pullup Resistors) - "It is recommended that the ADS# and LOCK# output terminals be connected to pullup resistors, as indicated in Table 5-2. The external pullups ensure that the signals remain negated during hold-acknowledge states." Table 5-2: 20k pullup resistor for each.

Other things. This is what I derived from reading everything on pipelining:
TI486SXL Pipeline support:
a) If Pipelining is supported, and the NA# pin (active low) is driven, the CPUs NA# pin should be connected & driven by the chipset.
b) If Pipelining is supported, and the NA# pin (active low) is NOT driven, the CPUs NA# pin should not be connected and should be pulled low with a 100-ohm resistor 0.5W.
c) If Pipelining is not supported, the CPUs NA# pin should not be connected and should be pulled high with a 10k/20k resistor.
d) If Pipelining is unknown, the CPUs NA# pin may be connected and pulled high with a 20k resistor.

I have a whole section on FLUSH/MEMW as well if interested.

Interested. Please share what you have, even if it is something covered previously. A fresh set of eyes is always nice.

These would be simple checks for others to make on their own motherboards. When I looked into this many years ago, I found a lack of consistency for the aforementioned pins on different 386 motherboards. I set out to standardise them across my 386 boards, but didn't notice much difference. Much of this is covered in this newsgroup print/scan I did ages ago. See attachment.

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Reply 1083 of 1247, by feipoa

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ChrisXF wrote on 2023-11-14, 13:56:

I haven't done much with pipelining, but iirc when I enabled it with the cyrix utility it did give a speed bump.

How much of a speed bump? I'm pretty sure I played with pipelining in CTCHIP34, but don't recall it having much of an impact. I guess we need to check the chipset datasheet to see if it supports this feature, then mod the board based on the information provided above.

Plan your life wisely, you'll be dead before you know it.

Reply 1085 of 1247, by Sphere478

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MikeSG wrote on 2023-11-14, 13:11:
There's a few lines in the manual about stability and using pullup resistors. Some mother boards may have them, some not... […]
Show full quote
ChrisXF wrote on 2023-11-12, 21:33:

I gave it a whizz from 33mhz to 40: that worked fine, but the moment clock doubling was switched on it hung.

There's a few lines in the manual about stability and using pullup resistors. Some mother boards may have them, some not...

I'm looking through the whole manual as I'm building my own interposer.

Page 197: (Hold acknowledge timing) Note 2 - "For maximum design flexibility the CPU has no internal pullup resistors on its outputs. External pullups may be required on ADS# and other outputs to keep them negated during hold-acknowledge period."
Page 208 (Terminals Requiring External Pullup Resistors) - "It is recommended that the ADS# and LOCK# output terminals be connected to pullup resistors, as indicated in Table 5-2. The external pullups ensure that the signals remain negated during hold-acknowledge states." Table 5-2: 20k pullup resistor for each.

Other things. This is what I derived from reading everything on pipelining:
TI486SXL Pipeline support:
a) If Pipelining is supported, and the NA# pin (active low) is driven, the CPUs NA# pin should be connected & driven by the chipset.
b) If Pipelining is supported, and the NA# pin (active low) is NOT driven, the CPUs NA# pin should not be connected and should be pulled low with a 100-ohm resistor 0.5W.
c) If Pipelining is not supported, the CPUs NA# pin should not be connected and should be pulled high with a 10k/20k resistor.
d) If Pipelining is unknown, the CPUs NA# pin may be connected and pulled high with a 20k resistor.

I have a whole section on FLUSH/MEMW as well if interested.

If we do some testing and determine which settings/resistors should be used (I mean if they help), we can probably make a guide on how to configure this without changing the interposer kind of like a socket mod, just solder the appropriate modification to the back of the interposer

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 1086 of 1247, by MikeSG

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I found all of the Cache Flush, Pipelining support (NA pin), and ADS/LOCK pins to be completely motherboard independant.

This is written for both PCB designer & end user. PCB solution underneath.

1) TI486SXL(C)2 Clock Doubling is enabled by software. "Cyrix.exe -cd"

2) TI486SXL(C) L1 Cache is enabled & flushed in the following ways:
-a) Cache Enable.
--i) If BIOS supports "Enable Cache", use this option.
--ii) If BIOS does not support "Enable Cache", Cache must be enabled by software. "Cyrix.exe -e"
-b) Cache flush.
--i) If the FLUSH# pin is supported by the chipset, FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
--ii) If the FLUSH# pin is not supported by the chipset:
---1) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is supported, enable BARB by software. "Cyrix.exe -b"
---2) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is NOT supported, solder a connection from MEMW# on the ISA bus/Cache-Memory Controller to the CPUs MEMW# pin (144/168-pin). FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
---3) If HOLD# is always sent to the CPU during DMA/master cycles, and Hidden Refresh is NOT supported, alternatively solder a connection from MEMW# on the ISA bus/Cache-Memory Controller to the CPUs FLUSH# pin (100/132/144/168-pin). Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
---4) If HOLD# is NOT always sent to the CPU during DMA/master cycles, and the system supports VLB (VESA Local Bus), enable BARB by software. "Cyrix.exe -b"
---5) If HOLD# is NOT always sent to the CPU during DMA/master cycles, and the system does NOT support VLB (VESA Local Bus), solder a NAND gate (two input-high, one output-low) where the two inputs are; an inverted MEMW# pin from the ISA bus/Cache-Memory Controller and the HLDA# pin from the Cache-Memory Controller, and the output is the CPUs FLUSH# pin. Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"
--iii) If MEMW# is NOT supported by the chipset, and it is unknown whether HOLD# is always sent during DMA/master cycles:
---1) Solder an OR gate (two input-low, one output-low) where the two inputs are; an inverted M/IO# pin and the W/R# or SO# pin, and the output is the CPUs FLUSH# pin. Leave the MEMW# pin on the CPU (144/168-pin) unconnected. FLUSH must be enabled and BARB must be disabled by software. "Cyrix.exe -b- -f"

3) TI486SXL Pipeline support:
-a) If Pipelining is supported, and the NA# pin (active low) is driven, the CPUs NA# pin should be connected & driven by the chipset.
-b) If Pipelining is supported, and the NA# pin (active low) is NOT driven, the CPUs NA# pin should not be connected and should be pulled low with a 100-ohm resistor 0.5W.
-c) If Pipelining is not supported, the CPUs NA# pin should not be connected and should be pulled high with a 10k/20k resistor.
-d) If Pipelining is unknown, the CPUs NA# pin may be connected and pulled high with a 20k resistor.

PCB SOLUTION:
CPU pin MEMW# - give a solder pad to the user
CPU pin FLUSH# - give a solder pad to the user
CPU pin FLUSH# - connect to output of 74LVC1G58 (multi combo function gate). Connect inputs to two set options. Use one only:
-Chipset MEMW# (active low), HLDA# (active high) - give solder pads to user
-Chipset SO# (active low), M/IO# (active high) - give solder pads to user
CPU pin NA# - give jumper selection to user
-no jumper - not connected, 10-20k pullup
-1-2 jumper - connected to 132pin socket, 10-20k pullup (default)
-2-3 jumper - not connected, 100-ohm (0.5w) pulldown

So the user needs look through their manual to see which features their motherboard supports to then select what to do with MEMW/FLUSH, and NA selection. MEMW# & FLUSH# have internal pullups. NA# does not. NA#, ADS# and LOCK# require pullups if the chipset doesn't have them, or a ~20k default pullup for all.

To my understanding, only 386 motherboards with an actual 486 socket support the FLUSH# pin directly. For all other boards you need to see what to do.

All of the information above is untested. From: https://usermanual.wiki/Document/1994TI486SXL … 1822911953/view

If right, the easiest boards (after 486 socketted boards) are boards with Hidden Refresh or VLB support, but you still need to make a choice for the NA# pin.

Last edited by MikeSG on 2023-11-16, 06:19. Edited 1 time in total.

Reply 1087 of 1247, by feipoa

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This is nice and concise. Thank you.

However, of the dozen or more 386 boards I've tested with a PGA132 SXL2 or DLC, I have always been able to get it working with BIOS options and cyrix.exe. Most of these boards were probably DLC aware, with no motherboards older than 1991. Thus I suspect your information may come in handy for those using older 386 motherboards.

The main problem I've run into was with the SXL2 clock-doubled when using DMA bust mastering SCSI controller (ISA), an AHA-154X, and on my oldest motherboard.

I will intend to play with this more when I do my SXL2-90 build, which is currently being held-up by a never-ending Am5x86-180 build. I've been engaged in this build on and off since early last spring.

Could you describe your test method for determining the state of HOLD# ?

Last edited by feipoa on 2023-11-15, 23:18. Edited 1 time in total.

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Reply 1088 of 1247, by Sphere478

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Ah interesting, I am using such a scsi card.

Good writeup MikeSG

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 1089 of 1247, by pshipkov

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To expand further on what Feipoa said about DLC/SXL2 and SCSI/EIDE bus mastering - it is problematic in general, across the board.
If it works here and there - that is the exception.
So the #HOLD nodes are very interesting.

retro bits and bytes

Reply 1090 of 1247, by MikeSG

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I have no idea how to test for how HOLD# is used.. but if you enable BARB and walk away (on all motherboards) there may be a performance hit as the internal cache is refreshed too often.

Most boards have a MEMW# line, so you can do three tests.
1) Leave MEMW# & FLUSH# on the CPU unconnected, turn on BARB in software. "Cyrix.exe -b". Test performance.
2) Connect MEMW# (from the ISA bus) to the CPUs MEMW# pin, turn off BARB & turn on FLUSH in software. "Cyrix.exe -b- -f". Test performance.
3) Connect MEMW# (from the ISA bus) to the CPUs FLUSH# pin, leave the CPUs MEMW# unconnected, turn off BARB & turn on FLUSH in software. "Cyrix.exe -b- -f". Test performance.

Use the highest performing method.

I only have one 386dx motherboard to test with, a Chips & Tech Peak-DM board with hidden refresh, crossing my fingers I only need BARB but, will probably do those three tests anyway. If you had a list of known chipsets that work a particular way you could create a definitive list of answers... otherwise it's trial & error.

Reply 1091 of 1247, by MikeSG

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I'm trying to get my own PCB design, components etc working by the end of the year. I'll post details if it works .. and put spares, instructions etc on eBay. All of the info above is all the theory I have... so hopefully that helps someone

Reply 1092 of 1247, by feipoa

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From my experience, BARB should work on nearly all motherboards, including the Peak-DM. I've reported on the BARB performance drop somewhere on Vogons - it was very small, in the ballpark of 1-3% in DOOM, if I recall correctly.

By the way, a solution to the issue with the DMA-based AHA-154X and SXL2 in clock doubled mde was to use BARB instead of FLUSH. It's almost perfect, but if I stress the system using IE5 in win3.11, I will eventually get HDD corruption, but only with IE5, and 1 in 10 times. On my [long] list is to replace the 154X with 152X on this system.

Will your PCB design be a whole new ground-up approach, or an adaption from a design already presented in this thread?

Plan your life wisely, you'll be dead before you know it.

Reply 1093 of 1247, by ChrisXF

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I suppose a fast'ish logic analyser (with logging) on one of the cache chips might show it being flushed with either method? May allow some idea of how often each method (barb or memw flush) dumps the cache on a set test.

Reply 1094 of 1247, by MikeSG

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feipoa wrote on 2023-11-16, 07:49:

I've reported on the BARB performance drop somewhere on Vogons - it was very small, in the ballpark of 1-3% in DOOM, if I recall correctly.

Will your PCB design be a whole new ground-up approach, or an adaption from a design already presented in this thread?

Slow Refresh/Hidden refresh may help to get some of that back. Slow Refresh gave me +4% performance on a 386sx.

The PCB design is new from the ground up. The CPU is actually rotated 180 degrees, but to not much benefit, about the same number of lines cross over.

ChrisXF wrote on 2023-11-16, 10:49:

I suppose a fast'ish logic analyser (with logging) on one of the cache chips might show it being flushed with either method? May allow some idea of how often each method (barb or memw flush) dumps the cache on a set test.

Possibly, but a chipset might deliberately keep the CPU out of the loop to save performance, and have separate HLD signals, one for the cache, one for the CPU.. I remember seeing something like that in the Peak-DM manual with hidden refresh... You could measure the HOLD# from the chipset/mem controller to the CPU, and MEMW... which ever is less updated, use that

Reply 1095 of 1247, by feipoa

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MikeSG wrote on 2023-11-16, 16:13:

The PCB design is new from the ground up. The CPU is actually rotated 180 degrees, but to not much benefit, about the same number of lines cross over.

Neat!

Yes, I noticed on the commercial units that the PGA132 and PGA168 were rotated by some factor, I think 180 degrees, but I felt it looked better and was less prone to insertion error if PGA132 and PGA168 were oriented the same with respect to pin 1.

I'll be interested to see your noise levels on Vin and Vout when it is finished. If you have any extra units, I'd be interested in comparing them.

Which VRM did you go with?

Are you planning on obtaining any quantity of the SXL2 CPUs for binning purposes? It seems like people are buying these up from online resources.

If I recall right, not having hidden refresh and using BARB was more like a 5% performance hit, but don't hold me to that value.

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Reply 1096 of 1247, by rasz_pl

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feipoa wrote on 2023-11-16, 07:49:

a solution to the issue with the DMA-based AHA-154X and SXL2 in clock doubled mde was to use BARB instead of FLUSH. It's almost perfect, but if I stress the system using IE5 in win3.11, I will eventually get HDD corruption

How would partition get corrupted with Write-Thru cache?
Write-Back mode has potential for DMA bus master ram read/HDD write going thru without CPU noticing and flushing cache in time, stale data lands on disk.
In Write-Thru corruption must happen during a HDD read/ram write. But since feipoa reports it works most of the time and only glitches in clock doubled mode it must be timing related? Connections are there, but signal has marginal timing? Alternatively cache flushing is fine and its CPU OC fault?

Open Source AT&T Globalyst/NCR/FIC 486-GAC-2 proprietary Cache Module reproduction

Reply 1097 of 1247, by feipoa

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rasz_pl wrote on 2023-11-17, 03:24:
How would partition get corrupted with Write-Thru cache? Write-Back mode has potential for DMA bus master ram read/HDD write goi […]
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feipoa wrote on 2023-11-16, 07:49:

a solution to the issue with the DMA-based AHA-154X and SXL2 in clock doubled mde was to use BARB instead of FLUSH. It's almost perfect, but if I stress the system using IE5 in win3.11, I will eventually get HDD corruption

How would partition get corrupted with Write-Thru cache?
Write-Back mode has potential for DMA bus master ram read/HDD write going thru without CPU noticing and flushing cache in time, stale data lands on disk.
In Write-Thru corruption must happen during a HDD read/ram write. But since feipoa reports it works most of the time and only glitches in clock doubled mode it must be timing related? Connections are there, but signal has marginal timing? Alternatively cache flushing is fine and its CPU OC fault?

Thanks for your interest in one of my ongoing vintage frustrations. The whole partition doesn't get corrupted, but usually a dozen or so [usually] system file names get all garbled up with unusual characters, so do their contents (e.g. system.ini). I cannot say for sure if this issue is due entirely to DMA SCSI on this particular setup, but I have been meaning to swap to a non-DMA SCSI controller to test. I know user pshipkov has run into similarly strange issues with DMA SCSI during his testing. The main deterant from me swapping the SCSI controller is the fact that I have 4 different operating systems (W3.11, W95, NT3.51, NT4) setup on one HDD and the overhaul will be difficult with the NT's. There's actually more to it than just that, like the complication with needing to boot to DOS first to load cyrix.exe files, then boot NT4. If interested, the solution was uncovered here: GRUB4DOS help needed to boot NT4 from DOS - SOLVED

This particular system, the AMI Mark V Baby Screamer has some odd issues, like not being able to clock double past 66 MHz, or being able to go up to 70 MHz if I limit the number of ISA cards. This issue was reported here: How to get 486 SXL2-66 to clock-double w/AMI Mark V Baby Screamer motherboard It has been a number of years since I looked into this. I recall someone saying the bus may be overloaded.

The issue with IE5 and HDD corruption was reported here: Internet Explorer 5 + Windows 3.11 + 386 It has also been a number of years since I looked into this. My solution was to uninstall IE5 so that I'm not tempted. IE5 works fine on other SXL2 systems.

The fact remains that I was able to use BARB with the AHA-154X (DMA SCSI controller) on this system, while I could use FLUSH with an AHA-152X. I'd have to check my notes for more specifics, but I'm not ready to re-dive into this issue right now.

Plan your life wisely, you'll be dead before you know it.

Reply 1098 of 1247, by MikeSG

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feipoa wrote on 2023-11-16, 17:26:

I'll be interested to see your noise levels on Vin and Vout when it is finished. If you have any extra units, I'd be interested in comparing them.

Which VRM did you go with?

Are you planning on obtaining any quantity of the SXL2 CPUs for binning purposes? It seems like people are buying these up from online resources.

VRM: I'm going with the AP7363-SP-13 (SO-8EP) at the moment. ..It's the only one that fits and can solder without a hot air gun. There's a bottom pad, but with an extended PCB pad and flux it should be fine. ~100mV volt drop at 1amp. Adjustable. 1.5A max load. https://www.diodes.com/assets/Datasheets/AP7363.pdf

I only have one SLX2-66 and can't really buy heaps and bin them right now.. but i'll for sure make spares available.. I just want to get one working first.

I don't know what to think about noise / capacitors. I upgraded a 386sx (33MHz) to a clock doubled ti486sxlc2-50 chip (66MHz)... zero added capacitors and everything works fine. Nevertheless I put a lot on the interposer. Pullups for ADS, LOCK, NA may be more important than VCC noise for stability... There's an acceptable voltage dip range in the manual, like 0.3v?

Reply 1099 of 1247, by feipoa

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The LDO I sourced has a dropout of about 150 mV at 1 A at 25 C, so similar specs in that regard. From a 5 V supply, I am able to adjust the output voltage up to about 4.95 V, which tends to indicate a nominal load of around 600 mA. Sorry, I forget the operating frequency for that load. I ran tests often in 1x mode because the noise was greater than in 2x mode, but I also tested up to 90 MHz.

I don't think a bucket load of filter caps are all that important. I went overboard on testing this. Even with Vout noises of around 425 mV, it was working fine from what I could discern. It was mentioned earlier on that I didn't think more than 4 - 8 Vcc3 caps were really necessary.

I'm looking forward to seeing a rendering of your PCB. Also looking forward to re-investigating the situation with ADS, LOCK, NA on various boards, just I have no time at present.

Plan your life wisely, you'll be dead before you know it.