Sorry if it seems like I was being accusatory or whatever, You’re good. I’m just trying to make sure we aren’t missing something. Throwing all the ideas out there. 😀 I’ve found doing multiple tests multiple ways with multiple measuring devices can sometimes reveal errant readings and false assumptions.

Start with the most probable, then fan out to the least probable.

Calamity strikes, setback averted!
I had a small setback recently, which happened after the latest tests, not before - so no worry about the test results. Remember that J1, VCC5 vs. VCC3 surface mount bridge jumper I didn't think we needed? Its presence came to haunt me today.

Let me explain what happened. To remove the VRM's, I need to use hot air. The desolder station just doesn't cut it here. So I have the 'third hand' alligator clip grab the tab of the VRM while I hot air the pins and pull the interposer with my hand. Unfortunately, due to the angle of hot air and gravity, the solder bridge I made over those J1 solder pads fell into the PGA pins (solder side) and shorted 3 pins together. I couldn't get the desodler station in there to suck the solder out. I tried my finest Weller tip + desolder station/pump, but couldn't get it out.

The only method I could think of which had a small chance of success would melt the ABS surrounding the pins. I decided I had nothing to loose because not being able to get that solder blob out renders the interposer useless. So I took my hot air gun and blew into the affected pins. After a time I felt sufficient to melt the solder, I took a can of compressed air and blew from the other end. Sure enough, the blob made its way out and the unit is still functional!

Something for you all to watch out for in your endeavours with these.

To help reduce the unsightly view of the pins, I decide to scrap it with a sharp blade to dull the burn marks and remove melt marks. I could probably improve upon it further with some 600 grit sand paper or the polish wheel on a dremel. All in all, I am relieved not to need to assemble another unit at this point. I have since installed a 0-ohm resistor in place of the solder bridge. I didn't take a photo of the blob, but here is one of the aftermath.

It’s funny, I was actually thinking that you should have used a 0 ohm resistor there earlier in the thread, but being a prototype it didn’t matter and there were more pressing issues 🤣.

A 0 0hm definitely looks nicer :p

I used a 0-ohm on Blavius' interposer, and when it didn't work, the comments were to 'try J1 at 3 V'. It is harder to move a resistor than a solder blob. So when I went to move Blavius' resistor, it flew off somewhere. So with the latest design, I was thinking 'I bet it won't work and everyone says to try J1 at 3V'. lol, this is why I used a solder blob on the new design. However, I don't know how much more damage proof the 0-ohm resistor is compared to the solder blob, thus when I go to hot air off the current VRM, I will need to watch for this repeat calamity closely. Notice how I left the leads long on the LP regulator - just to make it easier to remove.

I measured the resistance on my variable DC supply's cable from end to end: red was 2.8-ohms and black was 2.6-ohms. This explains the voltage drop witnessed. But I still got the 4.0 Vrms to the CPU by upping the voltage further. I think we can now safely eliminate the benchtop supply from the equation.

2.8 ohms is horrible.
Raising the voltage to compensate doesn’t fix the swing as load changes
Voltage will swing with higher resistance, and higher load

But if you feel you have eliminated it I won’t argue.

Just let me know if there is something you think we can change to make it better. You are the one in front of it not I

We aren't changing the load for the test with the variable DC supply. The load is the SXL CPU running at 40 MHz only and sitting at the DOS prompt. I have ensured the CPU is running at 4.00 Vrms by running the supply at 4.8 V. Yes, I can grab fatter cables and re-run the test, but when you see the 4.00V on the power supply be in agree with the 4.00 V on the scope and still see the 200 mV ripple, then what? The determination is the same. The increase in supply current needed to get 4.00 V to the CPU agrees with a the 0.8 V drop from a 2.5 ohm crappy cable. In my opinion, continuation with an external supply is barking up the wrong tree.

But your interest, I took the ends off on my crappy cable that came with my variable DC supply. While the cable cradding is thick, inside was only 28 AWG!

Sphere478 wrote on 2022-12-04, 03:33:

Just let me know if there is something you think we can change to make it better. You are the one in front of it not I

Determination of theoretical ideal values for adding 0805 ceramic caps between, say 8 of the PGA pins.

28awg… bruh,…

I feel duped. Look how thick the cladding is. I'm going to replace it with the black one, which is 16 AWG.

Excellent!

:p

Hopefully the internal wiring is up to snuff haha.

Feels like they were using the 3' cable as a fuse, lol

Before goofing around with adding caps around the PGA, I decided to run another test - adding a purely restive load without any data going through the interposer. I estimated around 700 mA going to the CPU at 80 MHz, and at 4 V, this is about 2.8 W. From the standpoint of Ohm's Law, the CPU is like a 5.7-ohm resistor. To determine the resistors to plug into the PGA, I first measured the nominal diameter of the PGA pins, it was 0.44 mm. But to use my 1 W or 2 W resistors, it would "stretch" the PGA female holes. So for what I have on hand, I needed to stick with some 1/2 W resistors and run several in parallel. To not exceed the wattage of each resistor, I added six 33-ohm resistors in parallel between VCC and GND. Six 33-ohm resistors in parallel is equivalent to 5.5-ohms, which is pretty close to the 5.7-ohm estimate from above. 2.8W / 6 = 0.47 watts per resistor. It is running in spec. I still hover a fan over the resistors while it is powered in the motherboard.

Low frequency noise is only 40 mV:

High frequency noise is around 8 mV:

I therefore conclude, and to confirm our suspicion, that the 200 mV noise witnessed earlier stems from funnelling data through the CPU/interposer. With a CPU installed and no data going through it, e.g. system stalled, the noise is not present. Since this noise is not evident with the Improve It + Gainbery device, we can conclude that there is an element lacking from the existing design. Next I will be play with cap placement next to the VCC3 and GND pins on the PGA underside. If anyone has recommendations for ideal capacitance, please share it with me soon. Failing this, another avenue would be with PCB redesign, but without additional conclusive insight, there would be little value in this.

feipoa wrote on 2022-12-04, 08:12:

With a CPU installed and no data going through it, e.g. system stalled, the noise is not present.

stalled how?
have you tried with ram uninstalled? hopefully CPU would still run executing instructions from Bios rom at that point looping in place

feipoa wrote on 2022-12-04, 08:12:

If anyone has recommendations for ideal capacitance, please share it with me soon.

can you measure whats on the commercial one? are those 10 or 100nF?
https://axotron.se/blog/inductance-of-some-de … upling-layouts/
http://axotron.se/blog/decoupling-primer/
https://axotron.se/blog/more-decoupling-layou … e-measurements/
parasitic inductance is what you get when connecting capacitors away from direct current path

Those look like fun reads, I'll try to get to them.

No, I haven't tried with the RAM removed. I can do that before I add caps to the PGA pins.

Stalled - if you get an NMI parity error for one. This might happen when the voltage is set too low and you clock double, like from 45 MHz to 90 MHz, then PARITY ERROR. I don't recall the exact error, but it was something like ROM... PARITY... ERROR. If it is important I can try to replicate it. Also, if I install my red prototype unit and try to run it at a frequency it doesn't care for, system won't turn on but the voltage readout on the scope is clean (low noise).

Yes, I am going to remove a cap on my Gainbery unit to measure it. I won't be desoldering any of the four ceramic caps from my exceedingly rare Evergreen SXL2-66 QFP adaptor.

Curious how this transcomputer modules which plug into a 486 and let you run an Am5x86 at 160 MHz, yet don't have any caps. And notice also how the Transcomputer module used a double through-hole approach, like the replica unit under test.

And how this IBM Blue Lightning interposer only has 2 ceramics around the CPU.

Makes me feel like the effort to solder these 10 caps onto the replica interposer will be fruitless. Anyway, I've mapped out the 10 most probably locations to solder caps to. In my bin, the caps I have which will fit are:

Ceramic
4x 33 pF 0805
8x 47 pF 0603
10x 220 pF 1206
20x 10 nF 1206
100x 10 nF 0603
100x 100 nF 0805
60x 10 uF 0805
9x 10 uF 1206

Tantalum
10x 10 uF 0805

I find the best fit is 0805, provided the existing soldering isn't to thick. Next best is 1206 because I can lay it sideways next to the pins. Worst is 0603, which is the smallest, and the gap between the cap and the through-hole pin might be a bit more difficult to fill with solder.

I de-soldered three non-adjacent capacitors on the bottom of the Gainbery VRM interposer. The measured values were: 80.5 nF, 96.7 nF, and 112 nF. I am guessing that they all were 100 nF nominally. If so, is this a standard amount of drift for multi-layer ceramic capacitors, or were these values very carefully selected by Gainbery?

feipoa wrote on 2022-12-04, 11:12:

Stalled - if you get an NMI parity error for one. This might happen when the voltage is set too low and you clock double, like from 45 MHz to 90 MHz, then PARITY ERROR. I don't recall the exact error, but it was something like ROM... PARITY... ERROR.

hmm, what would CPU do after generating that error message? 386s dont have any Idle instructions, maybe its looping in place in ram in its internal cache = no external CPU bus activity = no noise.
Noise at clock-in rate (2x cpu, 80MHz) would be from internal cpu computation, noise at half that is load from driving external bus. Imo its definitely not RFI inducted from data bus tracks overlapping power plane, its CPU pin drivers sipping power. I still dont know where that 1-2KHz comes from, is it some specific Chipset characteristic load pattern (dma, refresh, I dont really know)? is it the effect of cpu bus impedance on particular motherboard?

feipoa wrote on 2022-12-04, 11:12:

If it is important I can try to replicate it.

nah

feipoa wrote on 2022-12-04, 11:12:

Also, if I install my red prototype unit and try to run it at a frequency it doesn't care for, system won't turn on but the voltage readout on the scope is clean (low noise).

in that case I suspect cpu simply not starting, or hanging

feipoa wrote on 2022-12-04, 11:12:

Curious how this transcomputer modules which plug into a 486 and let you run an Am5x86 at 160 MHz, yet don't have any caps.

no power circuity, cpu power pins are directly pass thru

feipoa wrote on 2022-12-04, 11:12:

And how this IBM Blue Lightning interposer only has 2 ceramics around the CPU.

in same pattern as what I doodled 😀

main Cout cap C3 is on top of a trace going between regulator and cpu, there is no loop in the Vcc, and decoupling caps are on both sides of cpu close to VCC pins.

feipoa wrote on 2022-12-04, 11:12:

Makes me feel like the effort to solder these 10 caps onto the replica interposer will be fruitless.

makes me think direct opposite, still flood fill Vcc3 and those cap in the middle might make it not work.
1 keep that wire mod from before
2 remove caps from middle, you can solder them back on top of Cout
3 If its at all possible to reach you could try to scrape a gap in Vcc3 so it doesnt loop around, like the yellow line here:

using a thin sharp blade or something pointy. I have an old wing compass I use for scraping breaks in copper traces and unplugging pin holes

feipoa wrote on 2022-12-04, 11:12:

100x 100 nF 0805

perfect, you can start with just 4 caps one on each side ~in the middle

feipoa wrote on 2022-12-04, 11:45:

I de-soldered three non-adjacent capacitors on the bottom of the Gainbery VRM interposer. The measured values were: 80.5 nF, 96.7 nF, and 112 nF. I am guessing that they all were 100 nF nominally. If so, is this a standard amount of drift for multi-layer ceramic capacitors, or were these values very carefully selected by Gainbery?

yes, 20% tolerance is pretty standard

Although that Transcomputer unit is powered directly via the PSU, is that a sufficient reason for no caps? I've seen other interposers also without onboard voltage regulation and they did have caps. Is one vendor over engineering, or another under engineering?

On your marked up drawing, are you wanting all the red lines to be externally placed wire? That would require a lot of tedious effort. It would require cladded wire between the pins, and the looped wire would need to have burn spots on its cladding to make joints. It require making 23 little wires and delicately soldering them.

I was just going to add caps between 10 different VCC-to-GND pins directly. Is this that not sufficient?

If the red line is externally placed wire, I noticed that you want the VRM also connected such that the OUT pin is not in contact with the via below it. When I ran that test previously, it was in this configuration that the system would hang when trying to engage 2x mode.

For your yellow cut line, how far do I need to cut in? Are there any traces below which will be cut, e.g. data, address, control?

feipoa wrote on 2022-12-04, 13:39:

Although that Transcomputer unit is powered directly via the PSU, is that a sufficient reason for no caps? I've seen other interposers also without onboard voltage regulation and they did have caps. Is one vendor over engineering, or another under engineering?

hard to tell, but if power is generated externally its safe to not touch it as long as you provide direct connection, on the other hand Intel Slot1 adapters had shitton of capacitors, of course power requirements and tolerances changed dramatically at that point.

feipoa wrote on 2022-12-04, 13:39:

On your marked up drawing, are you wanting all the red lines to be externally placed wire?

no, I just drew to show overall desired layout/current path. Your plan of plopping caps between Vcc and Vss legs is perfect

feipoa wrote on 2022-12-04, 13:39:

I was just going to add caps between 10 different VCC-to-GND pins directly. Is this that not sufficient?

thats perfect, even half that would answer if thats what is missing

feipoa wrote on 2022-12-04, 13:39:

If the red line is externally placed wire, I noticed that you want the VRM also connected such that the OUT pin is not in contact with the via below it. When I ran that test previously, it was in this configuration that the system would hang when trying to engage 2x mode.

wait, did I miss you talking about hanging? All I saw was "no change". Thats weird 😮

feipoa wrote on 2022-12-04, 13:39:

For your yellow cut line, how far do I need to cut in? Are there any traces below which will be cut, e.g. data, address, control?

do you mean how deep? 1 layer deep 😀 as shallow as possible to just sever the surface copper track
Now that I think about it lets skip 1 and 3 and just do those caps 😀

It is the apparent lack of consistency with caps for 386 upgrades that is making me doubt the promise of providing more caps. I feel the caps added to 386 upgrades was a precautionary practice. However, I'm not so doubtful as not to try.

rasz_pl wrote on 2022-12-04, 14:08:

wait, did I miss you talking about hanging? All I saw was "no change". Thats weird :o

Nope, I didn't bring it up previously. The 'no change' is referring to the 1x noise level. I wasn't going to try 2x, but decided anyway. In my mind, 'noise the same, 2x crash - oh no!, time to move on'. Bug I guess I may need to re-wire it like it was previously, so there's more opportunity to troubleshoot.

I will,
1) test noise without RAM present, using LP as standard solder
2) add some 100 nF caps between PGA pins, using LP as standard solder
3) circumvent the wiring to Cout as before with LP first
4) same as 3 but with MIC
5) not cut the Vcc plane at yellow line

>using LP

LP? you mean bench supply?

>3) circumvent the wiring to Cout as before with LP first

if LP means external supply then you dont need to mod anything, just connect bench power supply at Cout

> not cut the Vcc plane at yellow line

yeah, better skip that, can end up with killed adapter without practice