The board will not POST without RTC. The RTC module is more than a button cell battery in black resin.

Hmmmm that thought crossed my mind but I was not sure if the RTC would prevent posting. I always thought it was only a battery but then again I'm quite noobish when it comes to retro.
I also removed the VCC jumpers since I don't find any info about it on that 'manual' I linked.
I think I mistook them for other jumpersettings so I hope I didn't fry something.
There is not much to be found about this board it seems.

Are the cache chips correct too?

So the only choice is to order an Odin RTC and hope it's not money thrown away 😀?

Skyscraper wrote:

The board will not POST without RTC. The RTC module is more than a button cell battery in black resin.

Exactly. No RTC means no CMOS. And it won't POST when no CMOS is present at all.

Stupid me....pfffff
Well I ordered 2 on Aliexpress.
Takes a month normally...
Will come back later on.

Are the cache chips ok?

Those cache chips seem.... off. They don't look quite right. You might need to disable the L2 cache to get it to post.

Will need to Google a bit then. I'm slowly learning.
This is how I Found the board. The chips are also smaller than the sockets. Weird no?

Is there a Page with more info on this board except for that bad scan 😀?
Seems like for some periods and or companies,info was lost or not decent documented.

Ik hope I didn't screw up with jumpering that vcc...

Murugan wrote:

Will need to Google a bit then. I'm slowly learning. This is how I Found the board. The chips are also smaller than the sockets. […]
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Will need to Google a bit then. I'm slowly learning.
This is how I Found the board. The chips are also smaller than the sockets. Weird no?

Is there a Page with more info on this board except for that bad scan 😀
Seems like for some periode and or companion,info was lost of decent documented.

Ik hope I didn't screw up with jumpering that vcc...

no, its normal. The longer sockets are for 512k and 1024k chips.

Thanks for the help and info so far.
This board can take max 1024k or so,so am I mistaken or are there even too much of these chips installed?

no, long story short, the chips are 256 K bits. So eight of them equal 256 K BYTES. Looking at your board, at the middle left, there is an empty space for a chip. left of the ISSI chip. These 2 chips are your TAG ram. You only have one 28-pin chip. So you are PRACTICALLY limited to 256k L2 (and 64mb of ram). If you populated the left chip with another 256Kb chip like teh ISSI one, then you can upgrade the cache past 256k.

Again, I'm glossing over MANY details. I'm sure you can google the details.

Will Google some more then.
It will take some time before I het the chips so I can study some more 😀
Thanks!

luckybob wrote:

no, long story short, the chips are 256 K bits. So eight of them equal 256 K BYTES. Looking at your board, at the middle left, there is an empty space for a chip. left of the ISSI chip. These 2 chips are your TAG ram. You only have one 28-pin chip. So you are PRACTICALLY limited to 256k L2 (and 64mb of ram). If you populated the left chip with another 256Kb chip like teh ISSI one, then you can upgrade the cache past 256k.

Again, I'm glossing over MANY details. I'm sure you can google the details.

I just checked the datasheet of SiS 85C501,

One 32K x 8bit tag ram is enough for 1M byte cache. The solder points on the left of the ISSI chip might be reserved for a 2M byte variant, or the dirty bit chip.

If you read the text at the bottom, without the dirty bit you are limited to HALF what the table says. So you only get 32mb with 256k. There are only 8 chip sockets so anything ending in x16 is not an option for this board.

So if you wanted 1mb L2 you need to fill that empty spot with a 32Kx1 chip.

luckybob wrote:

If you read the text at the bottom, without the dirty bit you are limited to HALF what the table says. So you only get 32mb with 256k. There are only 8 chip sockets so anything ending in x16 is not an option for this board.

So if you wanted 1mb L2 you need to fill that empty spot with a 32Kx1 chip.

Without the dirty chip the board can still work with 1M byte cache. The cacheable RAM is down to 64MB, which is still more than enough for any period correct application the board can handle.

Finally the ODIN RTC has arrived. Inserted it in the socket and yuy it works.
But now I'm trying to finish the build but I have no clue at all where to connect the HD and Turbo led. There are some open spots where reset,keylock etc are but I don't know what they do.
The link that I posted with the GIF shows nothing about these 2. I don't seem to find a more elaborate manual for this board.

Is there even a manual for this thing?

It looks a bit similar to this one:

http://stason.org/TULARC/pc/motherboards/C/CH … m-586SLM-3.html

Hmmmmm indeed it does! So weird that the jumper setting quick reference doesn't mention these 2 jumpers at all. If you look at the schematic I linked and the first picture, the amount of jumpers isn't even the same!
I just found the 5SLM (in another thread here mentioned together with the 5slb) and J23 might be one of the missing 2. I just don't want to fry this board 🤣. On both the 5slm and 586SLM.3, J23 is for the turbo led so I can pretty much accept that J23 will be the same here? J21 is on both boards for CPU speed selection but on the SLB it's JP10-11. And there is a JP21 too so will need to figure out what that is for.
Another look at the board tonight is on the menu and I'll take a pic to be sure.

I think this one is actually 'it'.
Seems Chaintech sometimes drops the "86" thus 586SLB becomes 5SLB
http://stason.org/TULARC/pc/motherboards/C/CH … ium-5SLB-1.html

It's indeed that board but there are jumpers on this board that are not on the picture nor mentioned anywhere. There is no information where to plug HD and turbo led.

Murugan wrote:

It's indeed that board but there are jumpers on this board that are not on the picture nor mentioned anywhere. There is no information where to plug HD and turbo led.

The HD LED connector is located at the right bottom of the last picture of the first post.