More information is required to answer your questions. Namely you need the datasheets for the dram and sram chips.

i may find the datasheet of the cache and dram chips, but don't all chips with same ratings have similar parameters?

Cache should be fine at 2-1-1-1

I would just do trial/error method to see how low you can get the other timings.

If it is unstable, then raise the last setting you changed.

If it fails to POST, reset the CMOS and the reset everything back to how it was before except for the one setting you changed that caused it to not POST.

The datasheets are not always going to be a sure-fire way to determine exactly how tight you can make the timings.

I think these are generally the timings that you "should" be able to get:

60ns FPM DRAM: 0WS at 33MHz, 1WS at 40MHz, 1WS at 50MHz, 2WS at 60MHz
70ns FPM DRAM: 0WS at 25MHz, 1WS at 33MHz, 1WS at 40MHz, 2WS at 50MHz
15ns SRAM: 2-1-1-1 at 33MHz, 3-1-1-1 at 40MHz, 3-2-2-2 at 50MHz
20ns SRAM: 2-1-1-1 at 25MHz, 3-1-1-1 at 33MHz, 3-2-2-2 at 40MHz

Sometimes 3-1-1-1 won't work but 2-2-2-2 will. 60ns RAM will often work with zero waitstates at 40MHz.

What happens on a 486 when there is a read that misses the L1 cache is that it reads a block of 16 bytes (4 32-bit words, this is the cache "line size") from the motherboard (whether that be L2 or RAM). So when you have 2-1-1-1 timing that means that it can read the first 32 bits in 2 cycles, and the next three reads take one cycle each. So reading 16 bytes from the L2 takes 5 bus cycles. If you have a DX2 CPU then 5 bus cycles equals 10 CPU cycles, and so on.

Reading from DRAM is usually 4-2-2-2 when you have it set at 0 WS. But it depends on the chipset. Once I had a 486-16 with 60ns RAM and no L2. It used 2-1-1-1 timing to access RAM.

On a 386 the cache line size could be different, since it is all handled off-chip. Who knows?

Sometimes you can work out what is going on from memory benchmarks. For instance, if you have a 486DX2-80, and you get 76MB/s for L1 and 38MB/s for L2, then you can figure 16 cycles for reading 16 bytes in the L1 (4 cycles for one LODSD instruction) plus an additional 16 cycles to read from L2, which is 8 bus cycles, which would suggest 2-2-2-2 timing...

It gets trickier though. RAM access can be interrupted by memory refresh, which would slightly lower the benchmark results. Some chipsets also have a huge penalty for L2 misses (turn off the L2 in the BIOS and your RAM performance can jump way up)

The "60ns" for 60ns FPM DRAM is the time for a random access (could be the first one in a series) but NOT including RAS precharge, which is sort of like a rest period. RAS precharge itself takes almost as long the stated access time (60ns), so at a minimum it might be 40-50ns. Consecutive memory access in the same page is faster, it takes half or less than the nominal 60ns, so it could be 20-30ns. So this is roughly how the timing breaks down for 4-2-2-2 at 33MHz. One cycle is 30ns. RAS precharge gets 2 cycles. First memory access is 2 cycles. Second, third, fourth are each 2 cycles. Why not one cycle for page mode read? Once the data is ready at the memory chip, it has to remain on the bus for a time so the CPU/chipset can read it before we can start the next read. (With EDO the cycles can overlap a bit, and 3-1-1-1 would be possible at 33MHz)

bakemono wrote:

I think these are generally the timings that you "should" be able to get:

thanks a lot man, that gives me much explanation.
but still, how are onboard cache srams accessed? async srams are usually rated -15ns, and a clock at 50mhz is 20ns, but why can't it do 2-1-1-1? even socket7 boards running at 100mhz require -5ns pbsram.

Yeah for some reason the access time has to be significantly faster than the time for one cycle. I don't know why specifically, I guess it has to do with lag caused by the chipset itself or the motherboard bus (capacitance)? Remember that when they moved the L2 cache right next to the CPU on slot 1 / slot a processors then it ran much faster, at half or 2/5 the cpu clock. Then they moved it right onto the die... but it still has a certain latency. I saw an article about cache latency on Core/Phenom CPUs here: https://www.anandtech.com/show/2702/5

bakemono wrote:

I think these are generally the timings that you "should" be able to get: […]
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I think these are generally the timings that you "should" be able to get:

60ns FPM DRAM: 0WS at 33MHz, 1WS at 40MHz, 1WS at 50MHz, 2WS at 60MHz
70ns FPM DRAM: 0WS at 25MHz, 1WS at 33MHz, 1WS at 40MHz, 2WS at 50MHz
15ns SRAM: 2-1-1-1 at 33MHz, 3-1-1-1 at 40MHz, 3-2-2-2 at 50MHz
20ns SRAM: 2-1-1-1 at 25MHz, 3-1-1-1 at 33MHz, 3-2-2-2 at 40MHz

Sometimes 3-1-1-1 won't work but 2-2-2-2 will. 60ns RAM will often work with zero waitstates at 40MHz.

This is a good post and explanation... I wouldn't be surprised if this matches your system.

Generally though, as mentioned, from system to system, it is a case of trial and error... though have no fear, this is all part of the fun! 😁