Anonymous Coward wrote:

I think he's just removing ICs from old SIMMs and soldering on NOS 40ns parts, probably 1Mbit density. What we really need is a new PCB using modern ICs.

I'm curious... when you say new PCB... what kind of board are you thinking of... i.e. 30-pin, 72-pin?

Also, what modern IC's are you meaning? How many bits wide are they?

The bus is not the limiting factor... it is the latency of the IC chips that determine system performance.

Both 70 and 60 ns are beyond capabilities of 386/486 anyway. But it's just easier to find 72 pin 486 motherboard instead of bothering with somewhat pricy and uncommon high density 30 pin SIMMs.

The Serpent Rider wrote:

The bus is not the limiting factor... it is the latency of the IC chips that determine system performance.

Both 70 and 60 ns are beyond capabilities of 386/486 anyway.

Why do you think this?

It takes only 30 ns to complete a cycle at 33MHz. Both 386 and 486 CPU's come in 33MHz (if not multiples of) and can execute a cycle every 30 ns... so why would 70 and 60 ns be beyond their capability?

Even one user here has a 286 with 45ns DIP chips. It runs at 30Mhz and 0-WS. 45ns SIMMs would be great in this case if he wanted more then 1MB of memory.

Why do you think this?

Because both were designed with Pentium/Pentium Pro FSB in mind (or at least 486DX 50mhz), which is 60/66 mhz. That's of course if we consider 30 and 72 pin SIMM timings universal and not entirely separate things.

The Serpent Rider wrote:

Why do you think this?

Because both were designed with Pentium/Pentium Pro FSB in mind (or at least 486DX 50mhz), which is 60/66 mhz. That's of course if we consider 30 and 72 pin SIMM timings universal and not entirely different thing.

This makes no sense!

30 pin SIMM's were designed for early 286 systems... up to and including 486 systems: -

https://en.wikipedia.org/wiki/SIMM

"The first variant of SIMMs has 30 pins and provides 8 bits of data (plus a 9th error-detection bit in parity SIMMs). They were used in AT-compatible (286-based, e.g., Wang APC[3]), 386-based, 486-based minicomputers."

The standard for 386 systems (apart from some early and SX systems) has always been any kind of 30 pin SIMM... which usually was 70ns.

The Serpent Rider wrote:

Both 70 and 60 ns are beyond capabilities of 386/486 anyway.

The statement above is nonsense, and totally untrue!

Given that a 386 or 486 is waaaaayyyyy much faster (multiple times over for a 486) than DRAM, it physically cannot be beyond their capability. DRAM is the bottleneck, not the 386 or 486!

You should try to understand and learn more about frequency and the affect of resulting wavelenths... i.e. RAM timings!

https://en.wikipedia.org/wiki/Frequency

It takes only 30 ns to complete a cycle at 33MHz

For example 25ns EDO memory is working at 100mhz (Voodoo 2).

This makes no sense!

Then what about practical tests?
And how would you explain that 50-60ns FPM/EDO has negligible difference compared to a SDRAM (66mhz an up)? Heck, even my Gigabyte Pentium Pro board (1996) is not aware of some fancy 30-40ns memory and has presets only up to 50ns.

You seem to be confused in your understanding which gives reason as to why you are so incoherent, unable to stay on topic and instead jumping around between various topics / examples.

You would be able to answer many of your own questions If you just took the time to try and understand this: -

https://en.wikipedia.org/wiki/Frequency

"For cyclical processes, such as rotation, oscillations, or waves, frequency is defined as a number of cycles per unit time. In physics and engineering disciplines, such as optics, acoustics, and radio, frequency is usually denoted by a Latin letter f or by the Greek letter {\displaystyle \nu } \nu or ν (nu) (see e.g. Planck's formula).

The relation between the frequency and the period {\displaystyle T} T of a repeating event or oscillation is given by

f = 1/T.... or... T = 1/f"

Once you understand and know the relationship between MHz and nanoseconds (ns) and convert between them... you will (hopefully) see things differently.

The Serpent Rider wrote:

And how would you explain

Since you are unable to see that the number 15 can be multiplied four times into 60, or that 60 can be divided by the number 15 four times...

it would be a fools errand to try and explain to you anything further as you are not in a position to be able to understand it.

1/66 = 15ns
DRAM = 60ns
60/15= 4!

386_junkie wrote:

Anonymous Coward wrote:

I think he's just removing ICs from old SIMMs and soldering on NOS 40ns parts, probably 1Mbit density. What we really need is a new PCB using modern ICs.

I'm curious... when you say new PCB... what kind of board are you thinking of... i.e. 30-pin, 72-pin?

Also, what modern IC's are you meaning? How many bits wide are they?

I think it would be better to start with a 72-pin SIMM, because in a 486 you only need to run 1 at a time vs four 30-pin SIMMs to get the full 32-bits.

I think getting modern DRAM working in an older maching is going to be troublesome. I wouldn't think that modern DDR SDRAM would work with a 486 memory controller unless there is additional support logic on the SIMM. I guess that is entirely possible, but definitely outside of my abilities. Using SRAM would probably be more straight forward. The problem is, they are still relatively expensive.

Is having too many datalines on an IC an absolute deal breaker? Would it be possible to use demultiplexers?

Anonymous Coward wrote:

I think it would be better to start with a 72-pin SIMM, because in a 486 you only need to run 1 at a time vs four 30-pin SIMMs to get the full 32-bits.

I think getting modern DRAM working in an older maching is going to be troublesome. I wouldn't think that modern DDR SDRAM would work with a 486 memory controller unless there is additional support logic on the SIMM. I guess that is entirely possible, but definitely outside of my abilities. Using SRAM would probably be more straight forward. The problem is, they are still relatively expensive.

I have not yet researched 72 pin technology such as traces and pin-out... but you are right, it may be easier to fab from scratch a new 72 rather than design and fab from scratch 4 x 30's.

I echo your sentiment regarding modern DRAM and would think that for 386/486 systems, we are limited to FPM/EDO IC's. Beyond these my knowledge of RAM becomes limited i.e. DDR SDRAM... additional support logic may be a difficult one to navigate depending on motherboard chipsets etc and if there is a way to process or mimic the signal? Outside of my abilities also. I looked into SRAM a while back and I found there was unfortunately some additional control logic that does not exist with DRAM, this... and the density issue meant I gave up on the idea.

Anonymous Coward wrote:

Is having too many datalines on an IC an absolute deal breaker? Would it be possible to use demultiplexers?

For a 30-pin SIMM, definitely a deal breaker... as a 16-bit IC can't be split between more than one SIMM, we're stuck with 8-bit wide IC's.

For a 72-pin SIMM, options are significantly greater as are the amount and type of IC's used. There also won't be the physical PCB limitations as there are with 30-pin SIMM's. Without knowing how to program PAL's/GAL's, I wouldn't look to use a demux, if I could avoid it... I would. Though using one... might allow the use of a typically unusable IC and in turn make for a more interesting SIMM!

Any muxes are going to eat away 10ns of headroom at least, if possible they should be avoided. Some PAL/GAL will most probably not do except at slower speeds (386 level), you absolutely need some CPLD to cope with the speed. DDR is never going to work, you'd have to implement a full blown memory controller there as they got strict minimum speed limits. SDRAM could be made to work if you run system clock to the module, running them asynchronously is not going to work without having access to a signal to stall the signal to get some favorabl alignment again between system and SDRAM clock.
One could make a dongle that has all the memory that is then exposed to the system via cables attaching to empty RAM slots. This could work with both 30 and 72pin machines also.
Are multiple memory banks common ? Bank = separate address and data lines per slot(group).

Would there be any change needed besides equipping a SIMM with faster ram chips - would lower BIOS values be enough to take advantage or would something more elaborate be required?

There will probably need to be some explicit overrides done in a later step by some smal util that programs the chipset with faster values than BIOS allows if that's even possible.

amadeus777999 wrote:

Would there be any change needed besides equipping a SIMM with faster ram chips - would lower BIOS values be enough to take advantage or would something more elaborate be required?

I cannot say for 72 pin SIMM's.... though no other change was needed for the 30-pin SIMM's I created. All I did using donor SIMM's, was remove the higher latency IC's and solder in new lower latency IC's... they went through the POST sequence fine, counted up the correct amount of memory, and were able to subsequently boot and be stable when BIOS timings were lowered to a point when previous tests using 60ns or 70ns SIMM's caused the system to become unstable and crash.

I would say the first batch that I made was more to test the theory, and in doing so I wasted quite a few number of donor SIMM's and IC's for various reasons. Now I know that modification of the 30 pin SIMM's work, when I have the time... I will be looking to create more. I have already bought and stockpiled literally hundreds upon hundreds of poor little donor SIMM's ready for surgery and have many tube's full of 40ns DRAM IC's.

What I would like to see though is for another user here on Vogons do a similar project... possibly a 72-pin SIMM? or maybe even a different higher density 30-pin SIMM that I have not considered? I'm happy to share thought's and idea's with anyone who is willing...

EDIT: -

I should also note that the testing of these SIMM's were limited to two different 386 motherboards... I have yet to test them on other systems, though don't see many reasons as to why they shouldn't be ok on other systems.